R8000 - Revision history

Ralf: /* Vaporware */

2009-02-26T15:26:39Z

‎Vaporware

Headless: /* Documentation files */

2007-10-31T17:17:47Z

‎Documentation files

Headless: /* Vaporware */

2007-10-31T17:16:03Z

‎Vaporware

Ralf: R8000 docs, finally!

2006-01-16T15:05:30Z

R8000 docs, finally!

Ddt at 17:17, 9 September 2005

2005-09-09T17:17:35Z

Ralf at 13:45, 2 January 2005

2005-01-02T13:45:11Z

Ralf: /* Vaporware */

2004-11-08T17:53:34Z

‎Vaporware

Ralf at 17:53, 8 November 2004

2004-11-08T17:53:25Z

Ralf at 17:49, 8 November 2004

2004-11-08T17:49:49Z

Ralf at 09:24, 4 November 2004

2004-11-04T09:24:29Z

New page

The '''R8000''' which was introduced in 1994 was the first [http://en.wikipedia.org/wiki/Superscalar superscalar] MIPS design, able to execute two ALU and two memory operations per cycle. The design was spread over six chips: an integer unit (with 16KB instruction and 16KB L1 data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4MB off-chip secondary cache. The R8000 powered SGI's Power Challenge computer servers in the mid 1990s and later became available in the Indigo2 Impact workstation. Its limited integer performance and high cost dampened appeal for most users, although its FPU performance fit scientific users quite well, and the R8000 was in the marketplace for only a year and remains fairly rare.

@@ Line 2: / Line 2: @@
 == Vaporware ==
-H1 or as it's codename was Beast was another high performance [[Instruction_Set_Architecture#MIPS_V|MIPS&nbsp;V]] microprocessor.  Little was known about the beast except it being designed by the same people that made the R8000.  Supposedly being a 12-issue processor would have made it's design an extremly ambitious project, probably again with a massive imbalance between integer and floating point performance.  Announced on [[May 12]]-[[1997]] its end along with its successor H2 codenamed Capitan was already announced on [[August 4]] of the same year.  Capitan was aiming at increasing memory bandwidth and scalability.  It's believed that axing these two projects was a good idea because of the extreme complexity of designing a new microprocessor from scratch.  The [[R10000]] successors did demonstrate that an evolutionary approach indeed can work well.
+H1 or as it's codename was Beast was another high performance [[Instruction_Set_Architecture#MIPS_V|MIPS&nbsp;V]] microprocessor.  Little was known about the beast except it being designed by the same people that made the R8000.  Supposedly being a 12-issue processor would have made it's design an extremly ambitious project, probably again with a massive imbalance between integer and [[floating point]] performance.  Announced on [[May 12]]-[[1997]] its end along with its successor H2 codenamed Capitan was already announced on [[August 4]] of the same year.  Capitan was aiming at increasing memory bandwidth and scalability.  It's believed that axing these two projects was a good idea because of the extreme complexity of designing a new microprocessor from scratch.  The [[R10000]] successors did demonstrate that an evolutionary approach indeed can work well.
 == Documentation ==

@@ Line 25: / Line 25: @@
 === Documentation files ===
-* http://www.linux-mips.org/pub/mips/docs/r8000/r8000-um.pdf<br>At this time unfortunately only paper compies of the R8000 manuals are available, so the electronic documents available here are PDFs created from 300dpi scans. We'll continue trying to obtain electronic copies of these documents and make them available on this page.  This is a 15MB PDF file primarily intended for printing.  It will display very slowly in all but the fastest pdf readers.
+* http://www.linux-mips.org/pub/mips/docs/r8000/r8000-um.pdf<br>At this time unfortunately only paper copies of the R8000 manuals are available, so the electronic documents available here are PDFs created from 300dpi scans. We'll continue trying to obtain electronic copies of these documents and make them available on this page.  This is a 15MB PDF file primarily intended for printing.  It will display very slowly in all but the fastest PDF readers.
-* http://www.linux-mips.org/pub/mips/docs/r8000/r8000-um.tar.bz2<br>This 35MB tarball contains the unprocessed 300dpi bw and greyscale scans.  Mostly here in case a bold soul wants to try to [[wikipedia:Optical_character_recognition|ocr]] the documents.
+* http://www.linux-mips.org/pub/mips/docs/r8000/r8000-um.tar.bz2<br>This 35MB tarball contains the unprocessed 300dpi b/w and greyscale scans.  Mostly here in case a bold soul wants to try to [[wikipedia:Optical_character_recognition|OCR]] the documents.

@@ Line 2: / Line 2: @@
 == Vaporware ==
-H1 or as it's codename was Beast was another highperformance [[Instruction_Set_Architecture#MIPS_V|MIPS&nbsp;V]] microprocessor.  Little was known about beast except it being designed by the same people that made the R8000.  Supposedly being a 12-issue processor would have made it's design an extremly ambitious project, probably again with a massive imballance between integer and floating point performance.  Announced on [[May 12]]-[[1997]] it's end along with it's successor H2 codenamed Capitan was already announced on [[August 4]] of the same year.  Capitan which was aiming at increasing memory bandwidth and scalability.  It's believed that axing these two projects was a good idea because of the extreme complexity of designing a new microprocessor from scratch.  The [[R10000]] successors did demonstrate that an evolutionary approach indeed can work well.
+H1 or as it's codename was Beast was another high performance [[Instruction_Set_Architecture#MIPS_V|MIPS&nbsp;V]] microprocessor.  Little was known about the beast except it being designed by the same people that made the R8000.  Supposedly being a 12-issue processor would have made it's design an extremly ambitious project, probably again with a massive imbalance between integer and floating point performance.  Announced on [[May 12]]-[[1997]] its end along with its successor H2 codenamed Capitan was already announced on [[August 4]] of the same year.  Capitan was aiming at increasing memory bandwidth and scalability.  It's believed that axing these two projects was a good idea because of the extreme complexity of designing a new microprocessor from scratch.  The [[R10000]] successors did demonstrate that an evolutionary approach indeed can work well.
 == Documentation ==

← Older revision		Revision as of 15:05, 16 January 2006
Line 3:		Line 3:
	== Vaporware ==		== Vaporware ==
	H1 or as it's codename was Beast was another highperformance [[Instruction_Set_Architecture#MIPS_V\|MIPS V]] microprocessor. Little was known about beast except it being designed by the same people that made the R8000. Supposedly being a 12-issue processor would have made it's design an extremly ambitious project, probably again with a massive imballance between integer and floating point performance. Announced on [[May 12]]-[[1997]] it's end along with it's successor H2 codenamed Capitan was already announced on [[August 4]] of the same year. Capitan which was aiming at increasing memory bandwidth and scalability. It's believed that axing these two projects was a good idea because of the extreme complexity of designing a new microprocessor from scratch. The [[R10000]] successors did demonstrate that an evolutionary approach indeed can work well.		H1 or as it's codename was Beast was another highperformance [[Instruction_Set_Architecture#MIPS_V\|MIPS V]] microprocessor. Little was known about beast except it being designed by the same people that made the R8000. Supposedly being a 12-issue processor would have made it's design an extremly ambitious project, probably again with a massive imballance between integer and floating point performance. Announced on [[May 12]]-[[1997]] it's end along with it's successor H2 codenamed Capitan was already announced on [[August 4]] of the same year. Capitan which was aiming at increasing memory bandwidth and scalability. It's believed that axing these two projects was a good idea because of the extreme complexity of designing a new microprocessor from scratch. The [[R10000]] successors did demonstrate that an evolutionary approach indeed can work well.
		+
		+	== Documentation ==
		+	In the spinout from SGI in [[1997]] [[MIPS Technologies]] inheritied the rights to the R8000 and eventually gave permission to distribute the R8000 documentation below.
		+
		+	=== Documentation license ===
		+	Copyright (c) 2004 MIPS Technologies, Inc.<br>
		+	All rights reserved.
		+
		+	Unpublished rights (if any) reserved under the copyright laws of the United States of America and other countries. The contents of this document may not be copied or duplicated in any form, in whole or in
		+	part, without the prior written permission of MIPS Technologies, Inc. ("MIPS Technologies").
		+
		+	MIPS Technologies does not assume any liability arising out of the application or use of this information, or of any error or omission in such information. Any warranties, whether express, statutory, implied
		+	or otherwise, including but not limited to the implied warranties of merchantability or fitness for a particular purpose, are excluded. Except as expressly provided in any written license agreement from
		+	MIPS Technologies, the furnishing of this document does not give recipient any license to any intellectual property rights, including any patent rights, that cover the information in this document.
		+
		+	The information contained in this document shall not be exported, reexported, transferred, or released, directly or indirectly, in violation of the law of any country or international law, regulation,
		+	treaty, Executive Order, statute, amendments or supplements thereto. Should a conflict arise regarding the export, reexport, transfer, or release of the information contained in this document, the laws of the United States of America shall be the governing law.
		+
		+	The information contained in this document constitutes one or more of the following: commercial computer software, commercial computer software documentation or other commercial items. If the user of this information, or any related documentation of any kind, including related technical data or manuals, is an agency, department, or other
		+	entity of the United States government ("Government"), the use, duplication, reproduction, release, modification, disclosure, or transfer of this information, or any related documentation of any kind, is restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of this information by the Government is further restricted in accordance with the terms of the license agreement(s) and/or applicable contract terms and conditions covering this information from MIPS Technologies.
		+
		+	=== Documentation files ===
		+	* http://www.linux-mips.org/pub/mips/docs/r8000/r8000-um.pdf<br>At this time unfortunately only paper compies of the R8000 manuals are available, so the electronic documents available here are PDFs created from 300dpi scans. We'll continue trying to obtain electronic copies of these documents and make them available on this page. This is a 15MB PDF file primarily intended for printing. It will display very slowly in all but the fastest pdf readers.
		+	* http://www.linux-mips.org/pub/mips/docs/r8000/r8000-um.tar.bz2<br>This 35MB tarball contains the unprocessed 300dpi bw and greyscale scans. Mostly here in case a bold soul wants to try to [[wikipedia:Optical_character_recognition\|ocr]] the documents.

@@ Line 1: / Line 1: @@
-The '''R8000''' which was introduced in 1994 was the first [http://en.wikipedia.org/wiki/Superscalar superscalar] MIPS design, able to execute two ALU and two memory operations per cycle. The design was spread over six chips: an integer unit (with 16KB instruction and 16KB L1 data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4MB off-chip secondary cache. The R8000 powered SGI's Power Challenge computer servers in the mid 1990s and later became available in the [[IP22|Indigo2]] Impact workstation. Its limited integer performance and high cost dampened appeal for most users, although its FPU performance fit scientific users quite well, and the R8000 was in the marketplace for only a year and remains fairly rare.
+The '''R8000''' which was introduced in 1994 was the first [http://en.wikipedia.org/wiki/Superscalar superscalar] MIPS design, able to execute two ALU and two memory operations per cycle. The design was spread over six chips: an integer unit (with 16KB instruction and 16KB L1 data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4MB off-chip secondary cache. The R8000 powered SGI's Power Challenge computer servers in the mid 1990s and later became available in the [[IP22|Indigo2]] Power workstation. Its limited integer performance and high cost dampened appeal for most users, although its FPU performance fit scientific users quite well, and the R8000 was in the marketplace for only a year and remains fairly rare.
 == Vaporware ==
 H1 or as it's codename was Beast was another highperformance [[Instruction_Set_Architecture#MIPS_V|MIPS&nbsp;V]] microprocessor.  Little was known about beast except it being designed by the same people that made the R8000.  Supposedly being a 12-issue processor would have made it's design an extremly ambitious project, probably again with a massive imballance between integer and floating point performance.  Announced on [[May 12]]-[[1997]] it's end along with it's successor H2 codenamed Capitan was already announced on [[August 4]] of the same year.  Capitan which was aiming at increasing memory bandwidth and scalability.  It's believed that axing these two projects was a good idea because of the extreme complexity of designing a new microprocessor from scratch.  The [[R10000]] successors did demonstrate that an evolutionary approach indeed can work well.

← Older revision		Revision as of 13:45, 2 January 2005
Line 2:		Line 2:

	== Vaporware ==		== Vaporware ==
−	H1 or as it's codename was Beast was another highperformance [[~~ISA~~\|MIPS V]] microprocessor. Little was known about beast except it being designed by the same people that made the R8000. Supposedly being a 12-issue processor would have made it's design an extremly ambitious project, probably again with a massive imballance between integer and floating point performance. Announced on [[May 12]]-[[1997]] it's end along with it's successor H2 codenamed Capitan was already announced on [[August 4]] of the same year. Capitan which was aiming at increasing memory bandwidth and scalability. It's believed that axing these two projects was a good idea because of the extreme complexity of designing a new microprocessor from scratch. The [[R10000]] successors did demonstrate that an evolutionary approach indeed can work well.	+	H1 or as it's codename was Beast was another highperformance [[Instruction_Set_Architecture#MIPS_V\|MIPS V]] microprocessor. Little was known about beast except it being designed by the same people that made the R8000. Supposedly being a 12-issue processor would have made it's design an extremly ambitious project, probably again with a massive imballance between integer and floating point performance. Announced on [[May 12]]-[[1997]] it's end along with it's successor H2 codenamed Capitan was already announced on [[August 4]] of the same year. Capitan which was aiming at increasing memory bandwidth and scalability. It's believed that axing these two projects was a good idea because of the extreme complexity of designing a new microprocessor from scratch. The [[R10000]] successors did demonstrate that an evolutionary approach indeed can work well.

← Older revision		Revision as of 17:53, 8 November 2004
Line 1:		Line 1:
	The '''R8000''' which was introduced in 1994 was the first [http://en.wikipedia.org/wiki/Superscalar superscalar] MIPS design, able to execute two ALU and two memory operations per cycle. The design was spread over six chips: an integer unit (with 16KB instruction and 16KB L1 data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4MB off-chip secondary cache. The R8000 powered SGI's Power Challenge computer servers in the mid 1990s and later became available in the [[IP22\|Indigo2]] Impact workstation. Its limited integer performance and high cost dampened appeal for most users, although its FPU performance fit scientific users quite well, and the R8000 was in the marketplace for only a year and remains fairly rare.		The '''R8000''' which was introduced in 1994 was the first [http://en.wikipedia.org/wiki/Superscalar superscalar] MIPS design, able to execute two ALU and two memory operations per cycle. The design was spread over six chips: an integer unit (with 16KB instruction and 16KB L1 data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4MB off-chip secondary cache. The R8000 powered SGI's Power Challenge computer servers in the mid 1990s and later became available in the [[IP22\|Indigo2]] Impact workstation. Its limited integer performance and high cost dampened appeal for most users, although its FPU performance fit scientific users quite well, and the R8000 was in the marketplace for only a year and remains fairly rare.

−	H1 or as it's codename was Beast was another highperformance [[ISA\|MIPS V] microprocessor. Little was known about beast except it being designed by the same people that made the R8000. Supposedly being a 12-issue processor would have made it's design an extremly ambitious project, probably again with a massive imballance between integer and floating point performance. Announced on [[May 12]]-[[1997]] it's end along with it's successor H2 codenamed Capitan was already announced on [[August 4]] of the same year. Capitan which was aiming at increasing memory bandwidth and scalability. It's believed that axing these two projects was a good idea because of the extreme complexity of designing a new microprocessor from scratch. The [[R10000]] successors did demonstrate that an evolutionary approach indeed can work well.	+	== Vaporware ===
		+	H1 or as it's codename was Beast was another highperformance [[ISA\|MIPS V]] microprocessor. Little was known about beast except it being designed by the same people that made the R8000. Supposedly being a 12-issue processor would have made it's design an extremly ambitious project, probably again with a massive imballance between integer and floating point performance. Announced on [[May 12]]-[[1997]] it's end along with it's successor H2 codenamed Capitan was already announced on [[August 4]] of the same year. Capitan which was aiming at increasing memory bandwidth and scalability. It's believed that axing these two projects was a good idea because of the extreme complexity of designing a new microprocessor from scratch. The [[R10000]] successors did demonstrate that an evolutionary approach indeed can work well.

← Older revision		Revision as of 17:49, 8 November 2004
Line 1:		Line 1:
−	The '''R8000''' which was introduced in 1994 was the first [http://en.wikipedia.org/wiki/Superscalar superscalar] MIPS design, able to execute two ALU and two memory operations per cycle. The design was spread over six chips: an integer unit (with 16KB instruction and 16KB L1 data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4MB off-chip secondary cache. The R8000 powered SGI's Power Challenge computer servers in the mid 1990s and later became available in the Indigo2 Impact workstation. Its limited integer performance and high cost dampened appeal for most users, although its FPU performance fit scientific users quite well, and the R8000 was in the marketplace for only a year and remains fairly rare.	+	The '''R8000''' which was introduced in 1994 was the first [http://en.wikipedia.org/wiki/Superscalar superscalar] MIPS design, able to execute two ALU and two memory operations per cycle. The design was spread over six chips: an integer unit (with 16KB instruction and 16KB L1 data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4MB off-chip secondary cache. The R8000 powered SGI's Power Challenge computer servers in the mid 1990s and later became available in the [[IP22\|Indigo2]] Impact workstation. Its limited integer performance and high cost dampened appeal for most users, although its FPU performance fit scientific users quite well, and the R8000 was in the marketplace for only a year and remains fairly rare.
		+
		+	H1 or as it's codename was Beast was another highperformance [[ISA\|MIPS V] microprocessor. Little was known about beast except it being designed by the same people that made the R8000. Supposedly being a 12-issue processor would have made it's design an extremly ambitious project, probably again with a massive imballance between integer and floating point performance. Announced on [[May 12]]-[[1997]] it's end along with it's successor H2 codenamed Capitan was already announced on [[August 4]] of the same year. Capitan which was aiming at increasing memory bandwidth and scalability. It's believed that axing these two projects was a good idea because of the extreme complexity of designing a new microprocessor from scratch. The [[R10000]] successors did demonstrate that an evolutionary approach indeed can work well.