Difference between revisions of "R8000"

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The '''R8000''' which was introduced in 1994 was the first [http://en.wikipedia.org/wiki/Superscalar superscalar] MIPS design, able to execute two ALU and two memory operations per cycle. The design was spread over six chips: an integer unit (with 16KB instruction and 16KB L1 data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4MB off-chip secondary cache. The R8000 powered SGI's Power Challenge computer servers in the mid 1990s and later became available in the Indigo2 Impact workstation. Its limited integer performance and high cost dampened appeal for most users, although its FPU performance fit scientific users quite well, and the R8000 was in the marketplace for only a year and remains fairly rare.
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The '''R8000''' which was introduced in 1994 was the first [http://en.wikipedia.org/wiki/Superscalar superscalar] MIPS design, able to execute two ALU and two memory operations per cycle. The design was spread over six chips: an integer unit (with 16KB instruction and 16KB L1 data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4MB off-chip secondary cache. The R8000 powered SGI's Power Challenge computer servers in the mid 1990s and later became available in the [[IP22|Indigo2]] Impact workstation. Its limited integer performance and high cost dampened appeal for most users, although its FPU performance fit scientific users quite well, and the R8000 was in the marketplace for only a year and remains fairly rare.
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H1 or as it's codename was Beast was another highperformance [[ISA|MIPS V] microprocessor.  Little was known about beast except it being designed by the same people that made the R8000.  Supposedly being a 12-issue processor would have made it's design an extremly ambitious project, probably again with a massive imballance between integer and floating point performance.  Announced on [[May 12]]-[[1997]] it's end along with it's successor H2 codenamed Capitan was already announced on [[August 4]] of the same year.  Capitan which was aiming at increasing memory bandwidth and scalability.  It's believed that axing these two projects was a good idea because of the extreme complexity of designing a new microprocessor from scratch.  The [[R10000]] successors did demonstrate that an evolutionary approach indeed can work well.

Revision as of 17:49, 8 November 2004

The R8000 which was introduced in 1994 was the first superscalar MIPS design, able to execute two ALU and two memory operations per cycle. The design was spread over six chips: an integer unit (with 16KB instruction and 16KB L1 data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4MB off-chip secondary cache. The R8000 powered SGI's Power Challenge computer servers in the mid 1990s and later became available in the Indigo2 Impact workstation. Its limited integer performance and high cost dampened appeal for most users, although its FPU performance fit scientific users quite well, and the R8000 was in the marketplace for only a year and remains fairly rare.

H1 or as it's codename was Beast was another highperformance [[ISA|MIPS V] microprocessor. Little was known about beast except it being designed by the same people that made the R8000. Supposedly being a 12-issue processor would have made it's design an extremly ambitious project, probably again with a massive imballance between integer and floating point performance. Announced on May 12-1997 it's end along with it's successor H2 codenamed Capitan was already announced on August 4 of the same year. Capitan which was aiming at increasing memory bandwidth and scalability. It's believed that axing these two projects was a good idea because of the extreme complexity of designing a new microprocessor from scratch. The R10000 successors did demonstrate that an evolutionary approach indeed can work well.