Difference between revisions of "R5900"
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| − | The R5900 | + | The R5900 is based on the [[TX79XX | TX79]] Toshiba Core and was developed by Toshiba, exclusively for use in the [[PS2|Playstation 2]] Emotion Engine (EE). It is similar to the [[R5000]], but adds several SIMD (multimedia) instructions. |
* It implements almost all [[Instruction_Set_Architecture#MIPS_III | MIPS3]] instructions, though it supports [[Instruction_Set_Architecture#MIPS_IV | MIPS4]]'s movn/movz. | * It implements almost all [[Instruction_Set_Architecture#MIPS_III | MIPS3]] instructions, though it supports [[Instruction_Set_Architecture#MIPS_IV | MIPS4]]'s movn/movz. | ||
| − | * | + | * 128-bit floating-point SIMD |
| + | * Multimedia extended instructions: 107 instructions at 128 bit width | ||
* It doesn't support load linked and store conditional instruction (ll/lld/sc/scd, MIPS2). | * It doesn't support load linked and store conditional instruction (ll/lld/sc/scd, MIPS2). | ||
| + | * COP0 hazard: mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p | ||
| + | * cache ops are original. | ||
| + | * single float FPU (IEEE754 not compatible) | ||
| + | * R4000 like MMU but 32bit mode only and scratch pad support. | ||
| + | * [[TLB]]: 48 double entries | ||
== External links == | == External links == | ||
* http://ps2dev.sourceforge.net/ | * http://ps2dev.sourceforge.net/ | ||
Revision as of 08:39, 5 May 2005
The R5900 is based on the TX79 Toshiba Core and was developed by Toshiba, exclusively for use in the Playstation 2 Emotion Engine (EE). It is similar to the R5000, but adds several SIMD (multimedia) instructions.
- It implements almost all MIPS3 instructions, though it supports MIPS4's movn/movz.
- 128-bit floating-point SIMD
- Multimedia extended instructions: 107 instructions at 128 bit width
- It doesn't support load linked and store conditional instruction (ll/lld/sc/scd, MIPS2).
- COP0 hazard: mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p
- cache ops are original.
- single float FPU (IEEE754 not compatible)
- R4000 like MMU but 32bit mode only and scratch pad support.
- TLB: 48 double entries
