R5000 - Revision history

Dmvo: /* SGI Indy specifics */

2008-10-23T22:26:01Z

‎SGI Indy specifics

Alec v: /* Variants */

2008-01-31T18:46:58Z

‎Variants

Alec v: /* Variants */

2008-01-31T18:44:59Z

‎Variants

KeithMann at 01:58, 3 June 2005

2005-06-03T01:58:10Z

KeithMann at 01:56, 3 June 2005

2005-06-03T01:56:27Z

Ralf at 18:10, 4 November 2004

2004-11-04T18:10:01Z

New page

== General ==
The '''R5000''' is a low-cost, dual-issue microprocessor with builtin FPU. Originally targeting the market of the [[R4600]] the market of the R5000 were low-cost RISC workstations and high-end embedded applications such as routers. It's 5-stage pipeline is architecturally similar to the R4600 but with 32kB instruction cache and 32kB data cache it's primary caches are twice as large. Another improvement over the R4600 is the integrated second level cache controller which reduces the access time over primary caches attached by an external second cache controller as it was done for a few R4600 systems such as the [[IP22|Silicon Graphics Indy]]. R5000 caches are not [[Coherency|coherent]].

== Variants ==
Targeting different cost ranges in embedded applications many variations of the original R5000 architecture were developed. Some reduce the [[SysAD|SysAD bus]] to just 32-bit for cost reasons, others half the cache sizes or eleminate the second level cache controller. Popular variants were the RM5230, RM5321, RM5260, RM5261 and RM5270 and RM5271, sometimes also known under the codename Nevada.

== SGI Indy specifics ==
R5000 processor modules for the [[IP22|Silicon Graphics Indy]] were available in several versions:

* 150MHz without second level cache controller
* 150MHz with 512kB of second level cache controlled by an external controller
* 180MHz with 512kB of second level cache controlled by an external controller

The external cache controller used is the same as for Indy [[R4600|R4600SC]] processor modules. That also means the internal second level cache controller of the R5000 is not used although would be faster. Presumably that was done because it simplified the design. The second level cache is not therefor requires special software support which Linux implements in sc-ip22.c.

← Older revision		Revision as of 22:26, 23 October 2008
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	* 180MHz with 512kB of second level cache controlled by an external controller		* 180MHz with 512kB of second level cache controlled by an external controller

−	The external cache controller used is the same as for Indy [[R4600\|R4600SC]] processor modules. That also means the internal second level cache controller of the R5000 is not used although would be faster. Presumably that was done because it simplified the design. The second level cache is not ~~therefor requires~~ special software support which Linux implements in sc-ip22.c.	+	The external cache controller used is the same as for Indy [[R4600\|R4600SC]] processor modules. That also means the internal second level cache controller of the R5000 is not used although would be faster. Presumably that was done because it simplified the design. The second level cache does not therefore require special software support which Linux implements in sc-ip22.c.

@@ Line 6: / Line 6: @@
 {| {{PrettyTable}}
-  !Model||I/D cache size||[[SysAD]] bus width||L2 cache||CPU Clockspeed||Package
+  !Model||I/D cache size||[[SysAD]] bus width||L2 cache interface||CPU Clockspeed||Package
   |-
   |RM5230||16/16||32||No||175MHz||128 PQuad

@@ Line 4: / Line 4: @@
 == Variants ==
 Targeting different cost ranges in embedded applications many variations of the original R5000 architecture were developed.  Some reduce the [[SysAD|SysAD bus]] to just 32-bit for cost reasons, others halve the cache sizes or eleminate the second level cache controller.  Popular variants were the RM5230, RM5321, RM5260, RM5261 and RM5270 and RM5271, sometimes also known under the codename Nevada.
 == SGI Indy specifics ==

@@ Line 1: / Line 1: @@
 == General ==
-The '''R5000''' is a low-cost, dual-issue microprocessor with builtin FPU.  Originally targeting the market of the [[R4600]] the market of the R5000 were low-cost RISC workstations and high-end embedded applications such as routers.  It's 5-stage pipeline is architecturally similar to the R4600 but with 32kB instruction cache and 32kB data cache its primary caches are twice as large.  Another improvement over the R4600 is the integrated second level cache controller which reduces the access time over primary caches attached by an external second cache controller as it was done for a few R4600 systems such as the [[IP22|Silicon Graphics Indy]].  R5000 caches are not [[Coherency|coherent]].
+The '''R5000''' is a low-cost, dual-issue microprocessor with builtin FPU.  Originally targeting the market of the [[R4600]] the market of the R5000 were low-cost RISC workstations and high-end embedded applications such as routers.  Its 5-stage pipeline is architecturally similar to the R4600 but with 32kB instruction cache and 32kB data cache its primary caches are twice as large.  Another improvement over the R4600 is the integrated second level cache controller which reduces the access time over primary caches attached by an external second cache controller as it was done for a few R4600 systems such as the [[IP22|Silicon Graphics Indy]].  R5000 caches are not [[Coherency|coherent]].
 == Variants ==
-Targeting different cost ranges in embedded applications many variations of the original R5000 architecture were developed.  Some reduce the [[SysAD|SysAD bus]] to just 32-bit for cost reasons, others half the cache sizes or eleminate the second level cache controller.  Popular variants were the RM5230, RM5321, RM5260, RM5261 and RM5270 and RM5271, sometimes also known under the codename Nevada.
+Targeting different cost ranges in embedded applications many variations of the original R5000 architecture were developed.  Some reduce the [[SysAD|SysAD bus]] to just 32-bit for cost reasons, others halve the cache sizes or eleminate the second level cache controller.  Popular variants were the RM5230, RM5321, RM5260, RM5261 and RM5270 and RM5271, sometimes also known under the codename Nevada.
 == SGI Indy specifics ==