R4600

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General

The R4600 started shipping in 1994 assthe first microprocessor developed by [[QED|Quantun Effect Devices, Inc.] and implements the MIPS III instruction set in a simple but effective 5-stage pipeline. It's very similar to the R4000 and R4400 processors but unlike these there is no integrated second level cache controller.

SGI Indy specifics

R4600 processor modules for the Silicon Graphics Indy were available in several versions:

  • 100MHz without second level cache controller
  • 100MHz with 512kB of second level cache controlled by an external controller
  • 133MHz with 512kB of second level cache controlled by an external controller

The external cache controller used is the same as for Indy R5000SC processor modules. It is not coherent therefore requires special software support which Linux implements in sc-ip22.c