R2000 - Revision history

Ralf: Mark article as stub.

2006-05-16T12:09:56Z

Mark article as stub.

Ralf: Rename ISA -> Instruction Set Architecture, make R3000 a link

2005-01-02T13:22:30Z

Rename ISA -> Instruction Set Architecture, make R3000 a link

Ralf at 13:53, 4 November 2004

2004-11-04T13:53:32Z

New page

The '''R2000''' is the first implementation of the MIPS architecture which started shipping in 1985. It features a 5 stage pipelines which implements the [[ISA|MIPS I]] instruction set. The '''R3000''' which started shipping in 1988 is almost identical but is running at a faster clock.

← Older revision		Revision as of 12:09, 16 May 2006
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	The '''R2000''' is the first implementation of the [[Wikipedia:MIPS_architecture\|MIPS architecture]] which started shipping in 1985. It features a 5 stage pipelines which implements the [[Instruction_Set_Architecture#MIPS_I\|MIPS I]] instruction set. The [[R3000]] which started shipping in 1988 is almost identical but is running at a faster clock.		The '''R2000''' is the first implementation of the [[Wikipedia:MIPS_architecture\|MIPS architecture]] which started shipping in 1985. It features a 5 stage pipelines which implements the [[Instruction_Set_Architecture#MIPS_I\|MIPS I]] instruction set. The [[R3000]] which started shipping in 1988 is almost identical but is running at a faster clock.

← Older revision		Revision as of 13:22, 2 January 2005
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−	The '''R2000''' is the first implementation of the MIPS architecture which started shipping in 1985. It features a 5 stage pipelines which implements the [[~~ISA~~\|MIPS I]] instruction set. The ~~'''~~R3000~~'''~~ which started shipping in 1988 is almost identical but is running at a faster clock.	+	The '''R2000''' is the first implementation of the [[Wikipedia:MIPS_architecture\|MIPS architecture]] which started shipping in 1985. It features a 5 stage pipelines which implements the [[Instruction_Set_Architecture#MIPS_I\|MIPS I]] instruction set. The [[R3000]] which started shipping in 1988 is almost identical but is running at a faster clock.