Difference between revisions of "R2000"
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The '''R2000''' is the first implementation of the [[Wikipedia:MIPS_architecture|MIPS architecture]] which started shipping in 1985. It features a 5 stage pipelines which implements the [[Instruction_Set_Architecture#MIPS_I|MIPS I]] instruction set. The [[R3000]] which started shipping in 1988 is almost identical but is running at a faster clock. | The '''R2000''' is the first implementation of the [[Wikipedia:MIPS_architecture|MIPS architecture]] which started shipping in 1985. It features a 5 stage pipelines which implements the [[Instruction_Set_Architecture#MIPS_I|MIPS I]] instruction set. The [[R3000]] which started shipping in 1988 is almost identical but is running at a faster clock. | ||
Latest revision as of 12:09, 16 May 2006
This article is a stub. You can help by expanding it
The R2000 is the first implementation of the MIPS architecture which started shipping in 1985. It features a 5 stage pipelines which implements the MIPS I instruction set. The R3000 which started shipping in 1988 is almost identical but is running at a faster clock.
