In 1995, MIPS released the R10000. This processor was a single-chip design, ran at a faster clock speed than the R8000, and had larger 32KB primary instruction and data caches. It was also superscalar, but its major innovation was out-of-order execution. Even with a single memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers.
More recent designs have all been built on the R10000 core. The R12000 used an improved process to shrink the chip and run it at higher clock rates. The R14000 bumped the speed again to up to 600MHz, added support for DDR] SRAM in the off-chip cache, and increased the SysAD bus speed to 200MHz for better throughput. The most recent version, the R16000, doubles the size of the caches to 64kB for both the instruction and data cache, adds support for up to 8MB of level 2 cache, and bumps the clock rates once again, to 700MHz.