R10000 - Revision history

Ralf: See also: Switch link to use permanent address

2012-08-16T20:16:36Z

See also: Switch link to use permanent address

Ralf: /* See also */ Use protocol independent URL.

2011-12-02T14:43:45Z

‎See also: Use protocol independent URL.

Ralf: Write a bit about the R10000 coherency issue

2004-11-18T13:02:14Z

Write a bit about the R10000 coherency issue

Ralf at 09:29, 4 November 2004

2004-11-04T09:29:51Z

New page

In 1995, MIPS released the '''R10000'''. This processor was a single-chip design, ran at a faster clock speed than the [[R8000]], and had larger 32KB primary instruction and data caches. It was also superscalar, but its major innovation was out-of-order execution. Even with a single memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers.

More recent designs have all been built on the R10000 core. The '''R12000''' used an improved process to shrink the chip and run it at higher clock rates. The '''R14000''' bumped the speed again to up to 600MHz, added support for [http://en.wikipedia.org/wiki/DDR_SDRAM DDR]] [http://en.wikipedia.org/wiki/SRAM SRAM] in the off-chip [http://en.wikipedia.org/wiki/CPU_cache cache], and increased the [[SysAD|SysAD bus]] speed to 200MHz for better throughput. The most recent version, the '''R16000''', doubles the size of the caches to 64kB for both the instruction and data cache, adds support for up to 8MB of level 2 cache, and bumps the clock rates once again, to 700MHz.

@@ Line 9: / Line 9: @@
 ==See also==
-* [//www.linux-mips.org/archives/linux-mips/1999-05/msg00019.html Issues with R10000 family processors in non-coherent systems]
+* [//www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=199905042300.QAA17970%40fir.engr.sgi.com Issues with R10000 family processors in non-coherent systems]
 * R12000 processor manual

@@ Line 9: / Line 9: @@
 ==See also==
-* http://www.linux-mips.org/archives/linux-mips/1999-05/msg00019.html
+* [//www.linux-mips.org/archives/linux-mips/1999-05/msg00019.html Issues with R10000 family processors in non-coherent systems]
 * R12000 processor manual

← Older revision		Revision as of 13:02, 18 November 2004
Line 1:		Line 1:
	In 1995, MIPS released the '''R10000'''. This processor was a single-chip design, ran at a faster clock speed than the [[R8000]], and had larger 32KB primary instruction and data caches. It was also superscalar, but its major innovation was out-of-order execution. Even with a single memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers.		In 1995, MIPS released the '''R10000'''. This processor was a single-chip design, ran at a faster clock speed than the [[R8000]], and had larger 32KB primary instruction and data caches. It was also superscalar, but its major innovation was out-of-order execution. Even with a single memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers.

−	More recent designs have all been built on the R10000 core. The '''R12000''' used an improved process to shrink the chip and run it at higher clock rates. The '''R14000''' bumped the speed again to up to 600MHz, added support for [~~http~~:~~//en.wikipedia.org/wiki/~~DDR_SDRAM DDR]] [~~http~~:~~//en.wikipedia.org/wiki/~~SRAM SRAM] in the off-chip [~~http~~:~~//en.wikipedia.org/wiki/~~CPU_cache cache], and increased the [[SysAD\|SysAD bus]] speed to 200MHz for better throughput. The most recent version, the '''R16000''', doubles the size of the caches to 64kB for both the instruction and data cache, adds support for up to 8MB of level 2 cache, and bumps the clock rates once again, to 700MHz.	+	More recent designs have all been built on the R10000 core. The '''R12000''' used an improved process to shrink the chip and run it at higher clock rates. The '''R14000''' bumped the speed again to up to 600MHz, added support for [[Wikipedia:DDR_SDRAM\|DDR]] [[Wikipedia:SRAM\|SRAM]] in the off-chip [[Wikipedia:CPU_cache\|cache]], and increased the [[SysAD\|SysAD bus]] speed to 200MHz for better throughput. The most recent version, the '''R16000''', doubles the size of the caches to 64kB for both the instruction and data cache, adds support for up to 8MB of level 2 cache, and bumps the clock rates once again, to 700MHz.
		+
		+	==R10000 family memory coherency issues==
		+	The R10000 features aggressive out of order execution including speculative execution of loads and stores. On systems with coherent I/O this does not pose a problem. On non-coherent systems this will cause serious memory corruption. Linux therefore currently does not support these systems. Affected systems are the [[IP22\|Indigo 2 R10000]] and all SGI [[IP32\|O2]] with R10000 family processors.
		+
		+	The issue exists in all R10000 family processors. R12000 and newer implement mode bit which faciliates a more efficient workaround but for unknown reasons this feature is not being used in the O2.
		+
		+	==See also==
		+	* http://www.linux-mips.org/archives/linux-mips/1999-05/msg00019.html
		+	* R12000 processor manual