QEMU

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Qemu is a generic open source processor and system emulator. It achieves good performance from using a Just-in-time compilation.

Processor

Qemu is simulating a range of processors, the standard selection is for the 32 bit emulation a 24Kf MIPS32 processor and for the 64 bit emulation a R4000 MIPS III processor.

$ qemu-system-mips64 -cpu '?'
MIPS '4Kc'
MIPS '4KEcR1'
MIPS '4KEc'
MIPS '24Kc'
MIPS '24Kf'
MIPS 'R4000'
MIPS '5Kc'
MIPS '5Kf'
MIPS '20Kc'

All processor emulations claim to have primary caches however the cache effects are not simulated and cacheops are treated as noops. This is a design decision to improve performance over accuracy. No benchmarking has been done however it is expected that the performance of the virtual MIPS system will be comparable to emulation of the other processors.

System architecture

Qemu 0.9.0 supports Mips Malta architecture with CoreLV card and mips pseudo-board.

$ qemu-system-mipsel -M ?
Supported machines are:
mips       mips r4k platform (default)
malta      MIPS Malta Core LV

This paragraph describes the architecture of the MIPS system (mips) that currently is being emulated by Qemu. As Qemu is still very much work in progress this is expected to change.

Firmware

The Qemu distribution does not contain any firmware for MIPS. This is only a minor problem as unlike on a real system Qemu's virtual hardware is mostly initialized after a reset.

At least some existing firmware for Mips Malta also works with Qemu, e.g. RedBoot. There is also a mmon port to the Qemu.

Memory map

Qemu emulates a simple machine with ISA-like bus. ISA IO space mapped to the 0x14000000 (PHYS) and ISA memory at the 0x10000000 (PHYS, 16Mb in size). All peripherial devices are attached to this "bus" with the standard PC ISA addresses.

Interrupt controller

Qemu is emulating the standard builtin interrrupt controller including soft interrupts and the count/compare interrupt of R4000-class processors. Cascaded externally to that is a i8259 PIC interrupt controller that is cascaded to the CPU's INT0.

Timer

In addition to the CPU builtin timer Linux support the i8254 PIT (Programmable Interval Timer) which is cascaded to the PIC's interrupt 0 input.

Graphics card

Qemu is emulating a standard VGA graphics card however underlined, bold and blinking attributes are not supported.

Serial interface

Qemu is emulating a PC-style 8250-based serial interface.

Network interface

Qemu is emulating a single ISA NE2000 network card.

Disk interface

Qemu emulates a generic PC-style IDE interface.

Other peripherals

Qemu supports other peripherals however support for them has not been integrated or tested into the MIPS port.

Status

At this time the MIPS support still is in alpha stage. There is not much firmware for Qemu yet, so Qemu does the basic initialization as well as loading kernel and ramdisk itself. The Linux kernel has a special configuration to support the Qemu platform, no additional patches are needed.

Debian installer images with such a kernel are available for big endian and little endian. They are also available on the Debian mirrors

A guide for installing Debian can be found here.

Common Problems

MIPS BIOS not found on startup

[ralf@box qemu]$ qemu-system-mips -kernel /tftboot/192.168.0.1/vmlinux.bin -m 16 -nographic
(qemu) mips_r4k_init: start
mips_r4k_init: load BIOS '/usr/local/share/qemu/mips_bios.bin' size 131072
qemu: could not load MIPS bios '/usr/local/share/qemu/mips_bios.bin'
[ralf@box qemu]$

There currently is no MIPS BIOS file for Qemu (see firmware). However if passed a -kernel argument qemu will not call the firmware at all, so this does no harm at all. Therefore, a command such as

dd if=/dev/zero of=/usr/local/share/qemu/mips_bios.bin bs=1024 count=128

will generate a firmware file that will do the job for now.

Since Qemu 0.8.1 this workaround is obsolete, a missing BIOS file triggers only a warning message.

MIPS HOST SUPPORT

In 2004, I successfully compiled QEMU on a SGI machine, using a patch found here:

http://libvncserver.sourceforge.net/qemu/

http://libvncserver.sourceforge.net/qemu/qemu-irix.patch.gz

I hope this patch could merge into the new qemu release. Thanks! -- Tinybit <tinybit at tom dot com>

See also

Credits

Originally authored by French wizzard Fabrice Bellard, Jocelyn Mayer did add support for MIPS as a target, others are now trying to complete the project.