P5600

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The P5600 is an IMG/MIPS 'Warrior P-class' licensable IP core implementing the MIPS32 Release 5 architecture specification including EVA, XPA, MSA and VZ, announced on 14th October 2013.

The P5600 follows on from the proAptiv line of MIPS IP cores, and implements a 16-stage wide-issue out of order pipeline. It delivers 3.5 DMIPS/MHz and 5 CoreMark/MHz.

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