Difference between revisions of "P5600"

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(Created page with "The P5600 is an IMG/MIPS 'Warrior P-class' licensable IP core implementing the MIPS32 Release 5 Architecture specification, announced on 14th October 2013. The P56...")
 
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The P5600 is an IMG/MIPS 'Warrior P-class' licensable IP core implementing the [[mips32|MIPS32 Release 5 Architecture]] specification, announced on 14th October 2013.
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The [[P5600]] is an IMG/MIPS 'Warrior P-class' licensable IP core implementing the [[MIPS32 Release 5]] architecture specification including [[EVA]], [[XPA]], [[MSA]] and [[VZ]], announced on 14th October 2013.
  
The P5600 follows on from the [[proAptiv|proAptiv]] line of MIPS IP cores, and implements a 16-stage wide-issue out of order pipeline. It delivers 3.5 DMIPS/MHz and 5 CoreMark/MHz.
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The P5600 follows on from the [[proAptiv]] line of MIPS IP cores, and implements a 16-stage wide-issue out of order pipeline. It delivers 3.5 DMIPS/MHz and 5 CoreMark/MHz.
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== See Also ==
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* [[proAptiv]]
  
 
== External Links ==
 
== External Links ==
[http://www.imgtec.com/mips/mips-series5-p5600.asp IMG P5600 home page]
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* [http://www.imgtec.com/mips/mips-series5-p5600.asp IMG P5600 home page]

Revision as of 22:57, 5 December 2013

The P5600 is an IMG/MIPS 'Warrior P-class' licensable IP core implementing the MIPS32 Release 5 architecture specification including EVA, XPA, MSA and VZ, announced on 14th October 2013.

The P5600 follows on from the proAptiv line of MIPS IP cores, and implements a 16-stage wide-issue out of order pipeline. It delivers 3.5 DMIPS/MHz and 5 CoreMark/MHz.

See Also

External Links