Difference between revisions of "NEC VR4121"

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{{CPU |
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Image= |
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Name=NEC V<sub>R</sub>4121 |
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Manufacturer=NEC |
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Core=V<sub>R</sub>4120 |
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Frequency=131 or 168 [[wikipedia:Megahertz|MHz]] |
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PICache=16 [[wikipedia:Kibibyte|KiB]] |
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PDCache=8 KiB |
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TLB=32 [[wikipedia:byte|bytes]] |
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Voltage= External: 3.0 to 3.6[[wikipedia:volt|V]]<br>Internal: 2.3 to 2.7V |
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Package= 224-pin, fine-pitch BGA
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}}
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The '''NEC V<sub>R</sub>4121''', which is a high-performance 64-/32-bit microprocessor employing the RISC (reduced instruction set computer) architecture developed by MIPS, is one of the RISC microprocessor V<sub>R</sub>-Series products manufactured by NEC.
 
The '''NEC V<sub>R</sub>4121''', which is a high-performance 64-/32-bit microprocessor employing the RISC (reduced instruction set computer) architecture developed by MIPS, is one of the RISC microprocessor V<sub>R</sub>-Series products manufactured by NEC.
  
 
The V<sub>R</sub>4121 consists of the ultra-low-power consumption V<sub>R</sub>4120&trade; CPU core with cache memory, high-speed product-sum operation unit, and address management unit. It also has interface units for the peripheral circuits, such as DMA, software modem interface, serial interface, keyboard interface, IrDA interface, touch panel interface, real-time clock, A/D converter, and D/A converter required for the battery-driven portable information equipment. The external bus width of this device can be selected between 32 bits and 16 bits and supports external devices that require the performance level of a color LCD controller.
 
The V<sub>R</sub>4121 consists of the ultra-low-power consumption V<sub>R</sub>4120&trade; CPU core with cache memory, high-speed product-sum operation unit, and address management unit. It also has interface units for the peripheral circuits, such as DMA, software modem interface, serial interface, keyboard interface, IrDA interface, touch panel interface, real-time clock, A/D converter, and D/A converter required for the battery-driven portable information equipment. The external bus width of this device can be selected between 32 bits and 16 bits and supports external devices that require the performance level of a color LCD controller.
  
This processor supports instruction set architecture (ISA) of [[MIPS I]], [[MIPS II]], [[MIPS III]], and [[MIPS16]]. It does not support LL, LLD, SC, SCD, and floating point instructions.
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This processor supports [[Instruction Set Architecture|instruction set architecture]] (ISA) of MIPS I, MIPS II, MIPS III, and [[MIPS16]]. It does not support LL, LLD, SC, SCD, and floating point instructions.
  
 
Note that this processor does not incorporate a secondary cache, multi-processor processing function, or floating point arithmetic function.
 
Note that this processor does not incorporate a secondary cache, multi-processor processing function, or floating point arithmetic function.

Revision as of 08:03, 29 January 2006

[[Image:|250px|A NEC VR4121]]
NEC VR4121
Manufacturer NEC
Core VR4120
Frequency 131 or 168 MHz
Primary Instruction cache 16 KiB
Primary Data cache 8 KiB
TLB entries 32 bytes
Supply Voltage External: 3.0 to 3.6V
Internal: 2.3 to 2.7V
Package 224-pin, fine-pitch BGA

The NEC VR4121, which is a high-performance 64-/32-bit microprocessor employing the RISC (reduced instruction set computer) architecture developed by MIPS, is one of the RISC microprocessor VR-Series products manufactured by NEC.

The VR4121 consists of the ultra-low-power consumption VR4120™ CPU core with cache memory, high-speed product-sum operation unit, and address management unit. It also has interface units for the peripheral circuits, such as DMA, software modem interface, serial interface, keyboard interface, IrDA interface, touch panel interface, real-time clock, A/D converter, and D/A converter required for the battery-driven portable information equipment. The external bus width of this device can be selected between 32 bits and 16 bits and supports external devices that require the performance level of a color LCD controller.

This processor supports instruction set architecture (ISA) of MIPS I, MIPS II, MIPS III, and MIPS16. It does not support LL, LLD, SC, SCD, and floating point instructions.

Note that this processor does not incorporate a secondary cache, multi-processor processing function, or floating point arithmetic function.

The features of the VR4121 are described below.

  • Employs 64-bit RISC CPU Core (VR4120 equivalent)
  • Internal 64-bit data processing
  • Optimized 6-stage pipeline
  • Conforms to MIPS I, II, III instruction sets (with the FPU, LL, LLD, SC, and SCD instructions left out)
  • Supports MIPS16 instruction
  • Supports high-speed product-sum operation instructions to execute applications in high speed
  • On-chip cache memory
    • Instruction cache: 16 Kbytes
    • Data cache: 8 Kbytes
  • Translation lookaside buffer (TLB) for virtual address management
  • Address space
    • Physical address space: 32 bits
    • Virtual address space: 40 bits
  • On-chip peripheral units suited for portable equipment
    • Memory controller (supports ROM, EDO-type DRAM, synchronous DRAM (SDRAM), synchronous ROM (SROM), and flash memory)
    • Supports ISA-bus interface
    • Keyboard interface
    • Touch panel interface (on-chip 4-channel A/D converter)
    • Controller complying with IrDA 1.1 (FIR)
    • Software modem interface supporting the HSP modem™ of PC-TEL
    • DMA controller
    • Serial interface
    • Debug serial interfaces
    • Interrupt controller
    • Audio interface (on-chip digital I/O, A/D and D/A converters)
    • General-purpose A/D converter: 3 channels
    • General-purpose ports
  • Effective power management features, which include the following four operating modes:
    • Full-speed mode: Normal operating mode in which all clocks operate
    • Standby mode: All internal clocks stop except for interrupt-related clocks
    • Suspend mode: Bus clock and all internal clocks stop except for interrupt-related clocks
    • Hibernate mode: All clocks generated by the CPU core stop
  • External input clock: 32.768 kHz, 18.432 MHz (for internal CPU core and peripheral unit operation), 48 MHz (dedicated for IrDA interface)
  • Clock supply management function for each on-chip peripheral unit to implement low-power consumption
  • Operation supply voltage: VDD2 = 2.5 V (internal), VDD3 = 3.3 V (external)