NEC VR4100 - Revision history

Ralf at 09:53, 14 October 2012

2012-10-14T09:53:37Z

2012-08-17T13:16:59Z

‎VR4101

2012-08-17T13:15:48Z

‎VR4181 / VR4181A

2012-08-17T13:15:34Z

‎VR4122

2012-08-17T13:14:49Z

‎VR4101

2009-02-26T15:25:57Z

‎VR4101

2007-05-26T20:21:52Z

2007-05-26T20:17:31Z

2007-04-21T20:42:24Z

‎Systems Using the VR4100 CPU

2006-06-28T04:54:38Z

‎Systems Using the VR4100 CPU

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 == VR4181 / VR4181A ==
 The VR4181A (µPD30181A) is a 131MHz 64-bit MIPS CPU that roughly implements the ([[Instruction_Set_Architecture#MIPS_III|MIPS III]] ISA, (without FPU, LL, and SC instructions) and [[MIPS16]]), plus interfaces for TFT/STN LCD display, dual CompactFlash, 3 UARTs, IrDA, I2C, 64 parallel I/O, RTC, watchdog timer, keyboard, USB, touch, audio I/O, and ISA-subset expansion bus.
 == Systems Using the VR4100 CPU ==

@@ Line 2: / Line 2: @@
 == VR4101 ==
-The VR4101 is a 64-bit microprocessor that implements the [[Instruction_Set_Architecture#MIPS_III]] ISA with [[MIPS16]] ASE make by NEC however it does not implement the <tt>LL</tt>, <tt>LLD</tt>, <tt>SC</tt> and <tt>SCD</tt> instructions nor an FPU.
+The VR4101 is a 64-bit microprocessor that implements the [[Instruction_Set_Architecture#MIPS_III|MIPS III]] ISA with [[MIPS16]] ASE make by NEC however it does not implement the <tt>LL</tt>, <tt>LLD</tt>, <tt>SC</tt> and <tt>SCD</tt> instructions nor an FPU.
 For application software Linux will emulate an FPU and the missing atomic load and store instructions so full compatibility with MIPS II and MIPS III software is provided.  For best performance however applications may need to

@@ Line 58: / Line 58: @@
 == VR4181 / VR4181A ==
-The VR4181A (ÂµPD30181A) is a 131MHz 64-bit MIPS CPU that roughly implements the ([[Instruction_Set_Architecture#MIPS_III|MIPS III]] ISA, (without FPU, LL, and SC instructions) and [[MIPS16]]), plus interfaces for TFT/STN LCD display, dual CompactFlash, 3 UARTs, IrDA, I2C, 64 parallel I/O, RTC, watchdog timer, keyboard, USB, touch, audio I/O, and ISA-subset expansion bus.
+The VR4181A (µPD30181A) is a 131MHz 64-bit MIPS CPU that roughly implements the ([[Instruction_Set_Architecture#MIPS_III|MIPS III]] ISA, (without FPU, LL, and SC instructions) and [[MIPS16]]), plus interfaces for TFT/STN LCD display, dual CompactFlash, 3 UARTs, IrDA, I2C, 64 parallel I/O, RTC, watchdog timer, keyboard, USB, touch, audio I/O, and ISA-subset expansion bus.
 == Systems Using the VR4100 CPU ==

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 == VR4122 ==
-The [[VR4122]] (ÂµPD30122) is one of NEC Electronicsâ€™ VR Series [[RISC]] microprocessors and is a high-performance 64-/32-bit microprocessor employing the MIPS RISC architecture.
+The [[VR4122]] (µPD30122) is one of NEC Electronics VR Series [[RISC]] microprocessors and is a high-performance 64-/32-bit microprocessor employing the MIPS RISC architecture.
 The VR4122 uses the high-performance, super power-saving VR4120 as the CPU core, and has many peripheral functions such as a DMA controller, serial interface, IrDA interface, and real-time clock. Configured with these functions, the VR4122 is suitable for high-speed battery-driven portable information systems. The external memory bus width can be selected from 32 bits and 16 bits, realizing high-speed data transfer.

@@ Line 2: / Line 2: @@
 == VR4101 ==
-The VR4101, which is a high-performance 64-/32-bit microprocessor employing the RISC (reduced instruction set computer) architecture developed by MIPS, is one of the RISC microprocessor VR-series products manufactured by NEC.
+The VR4101 is a 64-bit microprocessor that implements the [[Instruction_Set_Architecture#MIPS_III]] ISA with [[MIPS16]] ASE make by NEC however it does not implement the <tt>LL</tt>, <tt>LLD</tt>, <tt>SC</tt> and <tt>SCD</tt> instructions nor an FPU.
 The VR4101 consists of the low-power consumption VR4100; CPU core with cache memory, high-speed product-sum operation unit, and address management unit. It also has interface units for the peripheral circuits, such as DMA, software modem interface, serial interface, keyboard interface, IrDA interface, touch panel interface, real-time clock, A/D converter, and D/A converter required for the battery-driven portable information equipment. The external bus width of this device can be selected between 32 bits and 16 bits and supports external devices that require the performance level of a color LCD controller.
 == VR4102 ==

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 This processor supports [[Instruction Set Architecture|instruction set architecture]] (ISA) of MIPS I, MIPS II, MIPS III, and [[MIPS16]]. It does not support LL, LLD, SC, SCD, and floating point instructions.
-Note that this processor does not incorporate a secondary cache, multi-processor processing function, or floating point arithmetic function.
+Note that this processor does not incorporate a secondary cache, multi-processor processing function, or [[floating point]] arithmetic function.
 == VR4102 ==

@@ Line 68: / Line 68: @@
 * Vadem [[Clio]]
 * NEC MobilePro 780 [[MobilePro_780_%28MC-R530A%29]]
 * [[WorkPad z50]]

@@ Line 65: / Line 65: @@
 * [http://www.casio.co.jp/ppc/e55/ Casio E-55]
 * [http://www.casio.co.jp/ppc/e65/ Casio E-65]
-* CASIO Cassoipea E-105
+* CASIO Cassoipea E-100/E-105
 * Vadem [[Clio]]
 * NEC MobilePro 780 [[MobilePro_780_%28MC-R530A%29]]