Difference between revisions of "NEC VR4100"

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The VR4181A (µPD30181A) is a 131 MHz 64-bit MIPS CPU that roughly implements the ([[Instruction_Set_Architecture#MIPS_III|MIPS III]] ISA, (without FPU, LL, and SC instructions) and [[MIPS16]]), plus interfaces for TFT/STN LCD display, dual CompactFlash, 3 UARTs, IrDA, I2C, 64 parallel I/O, RTC, watchdog timer, keyboard, USB, touch, audio I/O, and ISA-subset expansion bus.
 
The VR4181A (µPD30181A) is a 131 MHz 64-bit MIPS CPU that roughly implements the ([[Instruction_Set_Architecture#MIPS_III|MIPS III]] ISA, (without FPU, LL, and SC instructions) and [[MIPS16]]), plus interfaces for TFT/STN LCD display, dual CompactFlash, 3 UARTs, IrDA, I2C, 64 parallel I/O, RTC, watchdog timer, keyboard, USB, touch, audio I/O, and ISA-subset expansion bus.
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== Datasheets ==
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Datasheets are available from [http://www.eu.necel.com/docuweb/ NEC Electronics] search page.
  
 
== External links ==
 
== External links ==
 
* http://www.linuxdevices.com/products/PD2831532191.html More on the VR4181A
 
* http://www.linuxdevices.com/products/PD2831532191.html More on the VR4181A
 
* http://www.necel.com/micro/english/product/vr/vr4100series/index.html Overview over the NEC VR4100 series
 
* http://www.necel.com/micro/english/product/vr/vr4100series/index.html Overview over the NEC VR4100 series
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* http://www.eu.necel.com/docuweb/ NEC Document database

Revision as of 10:13, 8 December 2005

NEC VR4133

VR4181A

The VR4181A (µPD30181A) is a 131 MHz 64-bit MIPS CPU that roughly implements the (MIPS III ISA, (without FPU, LL, and SC instructions) and MIPS16), plus interfaces for TFT/STN LCD display, dual CompactFlash, 3 UARTs, IrDA, I2C, 64 parallel I/O, RTC, watchdog timer, keyboard, USB, touch, audio I/O, and ISA-subset expansion bus.

Datasheets

Datasheets are available from NEC Electronics search page.

External links