Difference between revisions of "NEC VR4100"

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The '''NEC V<sub>R</sub>4100''' series of CPUs are based on the MIPS [[R4000]] core.
 
The '''NEC V<sub>R</sub>4100''' series of CPUs are based on the MIPS [[R4000]] core.
  
==[[NEC VR4121|V<sub>R</sub>4121]]==
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== [[NEC VR4121|V<sub>R</sub>4121]] ==
 
The V<sub>R</sub>4121, which is a high-performance 64-/32-bit microprocessor employing the RISC (reduced instruction set computer) architecture developed by MIPS, is one of the RISC microprocessor V<sub>R</sub>-Series products manufactured by NEC.
 
The V<sub>R</sub>4121, which is a high-performance 64-/32-bit microprocessor employing the RISC (reduced instruction set computer) architecture developed by MIPS, is one of the RISC microprocessor V<sub>R</sub>-Series products manufactured by NEC.
  
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Note that this processor does not incorporate a secondary cache, multi-processor processing function, or floating point arithmetic function.
 
Note that this processor does not incorporate a secondary cache, multi-processor processing function, or floating point arithmetic function.
  
==[[NEC VR4122|V<sub>R</sub>4122]]==
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== [[NEC VR4122|V<sub>R</sub>4122]] ==
==[[NEC VR4131|V<sub>R</sub>4131]]==
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== [[NEC VR4131|V<sub>R</sub>4131]] ==
==[[NEC VR4133|V<sub>R</sub>4133]]==
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== [[NEC VR4133|V<sub>R</sub>4133]] ==
  
 
The NEC VR4133 is a 200 Mhz processor with 16 KB of Primary Instruction cache and 16 KB of Primary Data cache. It has 32 TLB entries. The primary data cache line size is 32 bytes and the primary instruction cache line size is 32 bytes. Currently, this processor is fully supported in Linux versions 2.4 and 2.6.
 
The NEC VR4133 is a 200 Mhz processor with 16 KB of Primary Instruction cache and 16 KB of Primary Data cache. It has 32 TLB entries. The primary data cache line size is 32 bytes and the primary instruction cache line size is 32 bytes. Currently, this processor is fully supported in Linux versions 2.4 and 2.6.
  
==[[NEC VR4181|V<sub>R</sub>4181]]==
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== [[NEC VR4181|V<sub>R</sub>4181]] ==
==V<sub>R</sub>4181A==
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== V<sub>R</sub>4181A ==
  
  
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== Datasheets ==
 
== Datasheets ==
 
Datasheets are available from [http://www.eu.necel.com/docuweb/ NEC Electronics] search page.
 
Datasheets are available from [http://www.eu.necel.com/docuweb/ NEC Electronics] search page.
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== Systems Using the V<sub>R</sub>4100 CPU ==
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* [http://www.casio.co.jp/ppc/e55/ Casio E-55]
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* [http://www.casio.co.jp/ppc/e65/ Casio E-65]
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* CASIO Cassoipea E-105
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* Vadem [[Clio]]
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== See Also ==
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* [[Linux-VR]]
  
 
== External links ==
 
== External links ==
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* http://www.necel.com/micro/english/product/vr/vr4100series/index.html Overview over the NEC VR4100 series
 
* http://www.necel.com/micro/english/product/vr/vr4100series/index.html Overview over the NEC VR4100 series
 
* http://www.eu.necel.com/docuweb/ NEC Document database
 
* http://www.eu.necel.com/docuweb/ NEC Document database
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* [http://linux4.be Linux for the Casio BE-300]
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* [http://people.freebsd.org/~imp/pdamips.html Warner's Mips based PDA info Center]
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* NetBSD/[http://www.netbsd.org/Ports/hpcmips/ hpcmips] port.
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* [http://www.hacksrus.com/~mike/lince/lince-mips.htm Linux CE for MIPS-based Devices]

Revision as of 05:14, 29 January 2006

The NEC VR4100 series of CPUs are based on the MIPS R4000 core.

VR4121

The VR4121, which is a high-performance 64-/32-bit microprocessor employing the RISC (reduced instruction set computer) architecture developed by MIPS, is one of the RISC microprocessor VR-Series products manufactured by NEC.

The VR4121 consists of the ultra-low-power consumption VR4120™ CPU core with cache memory, high-speed product-sum operation unit, and address management unit. It also has interface units for the peripheral circuits, such as DMA, software modem interface, serial interface, keyboard interface, IrDA interface, touch panel interface, real-time clock, A/D converter, and D/A converter required for the battery-driven portable information equipment. The external bus width of this device can be selected between 32 bits and 16 bits and supports external devices that require the performance level of a color LCD controller.

This processor supports instruction set architecture (ISA) of MIPS I, MIPS II, MIPS III, and MIPS16. It does not support LL, LLD, SC, SCD, and floating point instructions.

Note that this processor does not incorporate a secondary cache, multi-processor processing function, or floating point arithmetic function.

VR4122

VR4131

VR4133

The NEC VR4133 is a 200 Mhz processor with 16 KB of Primary Instruction cache and 16 KB of Primary Data cache. It has 32 TLB entries. The primary data cache line size is 32 bytes and the primary instruction cache line size is 32 bytes. Currently, this processor is fully supported in Linux versions 2.4 and 2.6.

VR4181

VR4181A

The VR4181A (µPD30181A) is a 131 MHz 64-bit MIPS CPU that roughly implements the (MIPS III ISA, (without FPU, LL, and SC instructions) and MIPS16), plus interfaces for TFT/STN LCD display, dual CompactFlash, 3 UARTs, IrDA, I2C, 64 parallel I/O, RTC, watchdog timer, keyboard, USB, touch, audio I/O, and ISA-subset expansion bus.

Datasheets

Datasheets are available from NEC Electronics search page.

Systems Using the VR4100 CPU

See Also

External links