Difference between revisions of "NEC VR4100"

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The '''NEC V<sub>R</sub>4100''' series of CPUs are based on the MIPS [[R4000]] core.
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==V<sub>R</sub>4121==
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==V<sub>R</sub>4122==
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==V<sub>R</sub>4131==
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==V<sub>R</sub>4133==
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[[NEC VR4133]]
 
[[NEC VR4133]]
  
== VR4181A ==
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==V<sub>R</sub>4181==
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==V<sub>R</sub>4181A==
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The VR4181A (µPD30181A) is a 131 MHz 64-bit MIPS CPU that roughly implements the ([[Instruction_Set_Architecture#MIPS_III|MIPS III]] ISA, (without FPU, LL, and SC instructions) and [[MIPS16]]), plus interfaces for TFT/STN LCD display, dual CompactFlash, 3 UARTs, IrDA, I2C, 64 parallel I/O, RTC, watchdog timer, keyboard, USB, touch, audio I/O, and ISA-subset expansion bus.
 
The VR4181A (µPD30181A) is a 131 MHz 64-bit MIPS CPU that roughly implements the ([[Instruction_Set_Architecture#MIPS_III|MIPS III]] ISA, (without FPU, LL, and SC instructions) and [[MIPS16]]), plus interfaces for TFT/STN LCD display, dual CompactFlash, 3 UARTs, IrDA, I2C, 64 parallel I/O, RTC, watchdog timer, keyboard, USB, touch, audio I/O, and ISA-subset expansion bus.

Revision as of 19:44, 28 January 2006

The NEC VR4100 series of CPUs are based on the MIPS R4000 core.

VR4121

VR4122

VR4131

VR4133

NEC VR4133


VR4181

VR4181A

The VR4181A (µPD30181A) is a 131 MHz 64-bit MIPS CPU that roughly implements the (MIPS III ISA, (without FPU, LL, and SC instructions) and MIPS16), plus interfaces for TFT/STN LCD display, dual CompactFlash, 3 UARTs, IrDA, I2C, 64 parallel I/O, RTC, watchdog timer, keyboard, USB, touch, audio I/O, and ISA-subset expansion bus.

Datasheets

Datasheets are available from NEC Electronics search page.

External links