Difference between revisions of "MIPS1FPU"
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To do that, 16 double-precision registers each showed up as an even/odd pair of registers when loading, storing or moving data between integer and floating-point registers. | To do that, 16 double-precision registers each showed up as an even/odd pair of registers when loading, storing or moving data between integer and floating-point registers. | ||
| − | Later MIPS CPUs have 32 x 64-bit floating point registers, all usable for math operations. This is pretty incompatible, so they also have a mode bit ("Status[FR]" in the kernel-only-accessible "CP0" register set). Turn off FR, and your FPU look like an R2000's. | + | Later MIPS CPUs have 32 x 64-bit [[floating point]] registers, all usable for math operations. This is pretty incompatible, so they also have a mode bit ("Status[FR]" in the kernel-only-accessible "CP0" register set). Turn off FR, and your FPU look like an R2000's. |
There are now a small number of modern 32-bit MIPS CPUs (such as MIPS Technologies' 24Kf core) with FPU hardware. But all of them have a grown up 32 x 64 register set. | There are now a small number of modern 32-bit MIPS CPUs (such as MIPS Technologies' 24Kf core) with FPU hardware. But all of them have a grown up 32 x 64 register set. | ||
Because the first CPU to have a grown-up FPU was the R4000, which was also the first 64-bit MIPS CPU, some people use the shorthand "32-bit FPU" to describe the MIPS I arrangement. That's wrong, because MIPS I had double-precision hardware. It's worse than wrong, because a few errant MIPS CPUs really have been built with single-precision-only FPU hardware. | Because the first CPU to have a grown-up FPU was the R4000, which was also the first 64-bit MIPS CPU, some people use the shorthand "32-bit FPU" to describe the MIPS I arrangement. That's wrong, because MIPS I had double-precision hardware. It's worse than wrong, because a few errant MIPS CPUs really have been built with single-precision-only FPU hardware. | ||
Latest revision as of 15:23, 26 February 2009
[edit] MIPS I Floating Point Model
MIPS I CPUs (starting with R2000) were 32-bit integer CPUs fitted with FPU hardware which supported 32-bit (single-precision) and 64-bit (double-precision) floating point formats, even though all the input and output connections of the FPU were 32 bits wide.
To do that, 16 double-precision registers each showed up as an even/odd pair of registers when loading, storing or moving data between integer and floating-point registers.
Later MIPS CPUs have 32 x 64-bit floating point registers, all usable for math operations. This is pretty incompatible, so they also have a mode bit ("Status[FR]" in the kernel-only-accessible "CP0" register set). Turn off FR, and your FPU look like an R2000's.
There are now a small number of modern 32-bit MIPS CPUs (such as MIPS Technologies' 24Kf core) with FPU hardware. But all of them have a grown up 32 x 64 register set.
Because the first CPU to have a grown-up FPU was the R4000, which was also the first 64-bit MIPS CPU, some people use the shorthand "32-bit FPU" to describe the MIPS I arrangement. That's wrong, because MIPS I had double-precision hardware. It's worse than wrong, because a few errant MIPS CPUs really have been built with single-precision-only FPU hardware.
