Difference between revisions of "Loongson"

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(Loongson 2E)
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Loongson 2E was designed by ICT (Institute of Computing Technology), a department of The Chinese Academy of Sciences, helped and manufactured by STMicroelectronics.
 
Loongson 2E was designed by ICT (Institute of Computing Technology), a department of The Chinese Academy of Sciences, helped and manufactured by STMicroelectronics.
  
This processor is a design of MIPSIII RISC cpu, which has separate 64KB L1 data and instruction caches. Like
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'''ST Generic Part Number:''' STLS2E02
R10000 Family, it is also a superscalar with out-of-order execution. With On-chip 512KB L2 cache ,fast FPU and a DDR controller the processor runs at 600MHz - 800MHz.
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'''Features'''
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'''Microarchitecture:'''
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- 64 bit
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- 9 pipeline stages
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- 4-issue Out-Of-Order Executive
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- 2 ALU, 2 FALU, 1 SIMD, 1 Load/Store Units
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'''ISA:''' MIPSIII
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'''Cache:''' 64KB L1 date, 64KB L1 instruction, on-chip 512KB L2.
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'''Clock Frequence:''' 600MHz - 800MHz.
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'''TDP:''' 4 Watt at 700MHz
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'''Integrated:''' DDR-333 memory controller.
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'''High Lights'''
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ST's Leading Edge 90nm process.
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Some new instructions: Allow write to register directly without MFLO or MFHI.
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Some new instructions: MADD.[S|D] MSUB.[S|D] NMADD.[S|D] NMSUB.[S|D].
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Some new SIMD instructions: simmilar to MMX, using FPU for parallel fix-point arithmetic.
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An Executive bit: help OS to protect from buffer-flow attack.
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The following 2F is under manufacture(July,2007) which has a higher frequence, an on-chip DDR2 controller and advanced power control technology.
 
The following 2F is under manufacture(July,2007) which has a higher frequence, an on-chip DDR2 controller and advanced power control technology.
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* http://www.loongson.cn/
 
* http://www.loongson.cn/

Revision as of 01:34, 14 August 2007

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Loongson 2E

Loongson 2E is the latest processor in Loongson 2 Family. Loongson 2E was designed by ICT (Institute of Computing Technology), a department of The Chinese Academy of Sciences, helped and manufactured by STMicroelectronics.

ST Generic Part Number: STLS2E02

Features

Microarchitecture: - 64 bit - 9 pipeline stages - 4-issue Out-Of-Order Executive - 2 ALU, 2 FALU, 1 SIMD, 1 Load/Store Units

ISA: MIPSIII

Cache: 64KB L1 date, 64KB L1 instruction, on-chip 512KB L2.

Clock Frequence: 600MHz - 800MHz.

TDP: 4 Watt at 700MHz

Integrated: DDR-333 memory controller.


High Lights

ST's Leading Edge 90nm process.

Some new instructions: Allow write to register directly without MFLO or MFHI.

Some new instructions: MADD.[S|D] MSUB.[S|D] NMADD.[S|D] NMSUB.[S|D].

Some new SIMD instructions: simmilar to MMX, using FPU for parallel fix-point arithmetic.

An Executive bit: help OS to protect from buffer-flow attack.



The following 2F is under manufacture(July,2007) which has a higher frequence, an on-chip DDR2 controller and advanced power control technology.


Devices based on this CPU

Processor documentation

Chinese version

English version