Difference between revisions of "JTAG"

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== (E)JTAG in general ==
 
== (E)JTAG in general ==
  
Most of modern MIPS [[SoC]]s support [[Wikipedia:JTAG|JTAG]] (IEEE 1149.1). The MIPS [http://www.mips.com/content/Documentation/MIPSDocumentation/EJTAG/doclibrary EJTAG] is a proprietary extension which utilizes widely used IEEE JTAG pins for debug functions. EJTAG provides: run control, breakpoints on both data and instructions, real-time trace and direct memory access.
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Most of modern MIPS [[SOC]]s support [[Wikipedia:JTAG|JTAG]] (IEEE 1149.1). The MIPS [http://www.mips.com/content/Documentation/MIPSDocumentation/EJTAG/doclibrary EJTAG] is a proprietary extension which utilizes widely used IEEE JTAG pins for debug functions. EJTAG provides: run control, single-step execution, breakpoints on both data and instructions, real-time trace (optional) and direct memory access.
  
The EJTAG prior v2.6 was not documented, however many SoCs still use it. The v2.6 is fully documented and available on the MIPS site (''free'' registration required). The IMPCODE register contains EJTAGver field, software should read it to distinguish EJTAG version.
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The EJTAG prior v2.6 was not documented, however many SOCs still use it. The v2.6 is fully documented and available on the MIPS site (''free'' registration required). The IMPCODE register contains EJTAGver field, so software should read it to distinguish EJTAG version.
  
 
MIPS EJTAG has two modes, one is "DMA" mode where the JTAG can cause CPU bus cycles directly, the other "PrAcc" is where the JTAG interface is used to respond to CPU memory accesses in a special range of memory (DMSEG, 0xFF200000) and you have to write little bits of MIPS code to do what you want and emulate that memory on the host side. All systems support PrAcc mode by nature. The DMA mode is optional and not as widely supported as the normal mode. The presence of DMA mode is noted in the IMPCODE register.
 
MIPS EJTAG has two modes, one is "DMA" mode where the JTAG can cause CPU bus cycles directly, the other "PrAcc" is where the JTAG interface is used to respond to CPU memory accesses in a special range of memory (DMSEG, 0xFF200000) and you have to write little bits of MIPS code to do what you want and emulate that memory on the host side. All systems support PrAcc mode by nature. The DMA mode is optional and not as widely supported as the normal mode. The presence of DMA mode is noted in the IMPCODE register.
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== JTAG header ==
 
== JTAG header ==
  
EJTAG utilizes IEEE 1149.1 JTAG specification for off-chip communications.
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EJTAG utilizes 5-pin interface defined in IEEE 1149.1 JTAG specification for off-chip communications. These signals (TDI, TDO, TMS, TCK and nTRST) forms a Test Access Port (TAP). EJTAG 2.6 defines a 14-pin header (mechanical connector) to attach a JTAG probe.
  
 
  nTRST  1  2 GND
 
  nTRST  1  2 GND
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  DINT  13 14 VCC
 
  DINT  13 14 VCC
  
DINT pin is not used.
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'''DINT''' pin is used to raise Debug Interrupt. Many chips has no this pin.
  
nTRST is a "TAP Reset" signal and it's active level is "0" (the first "n" indicates negative logic). nSRST is optional. This signal resets TAP controller independently from the CPU logic. To conform to MIPS EJTAG specifications this pin should be pulled to the ground via resistor ~1KOhm to keep TAP in reset state w/o probe attached. If probe does not control this pin, you need just to feed logical "1" to nTRST pin or pull this to the +VCC via ~300Ohm resistor.
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'''nTRST''' is a "TAP Reset" signal and it's active level is "0" (the first "n" indicates negative logic). nSRST is optional. This signal resets TAP controller independently from the CPU logic. To conform to MIPS EJTAG specifications this pin should be pulled to the ground via resistor ~1KOhm to keep TAP in reset state w/o probe attached. If probe does not control this pin, you need just to feed logical "1" to nTRST pin or pull this to the +VCC via ~300Ohm resistor.
 
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nSRST is a "system reset" signal and acts like conventional "Reset' button.
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'''nSRST''' is a "system reset" signal and acts like conventional "Reset' button.
  
 
== (E)JTAG Cables ==
 
== (E)JTAG Cables ==
There is a page at the OpenWrt Wiki that discusses [http://wiki.openwrt.org/JTAG_Cables JTAG cables].  Specifically, how one Wiggler-style buffered cable can be used for both ADM5120-based routers (e.g. Edimax) and Broadcom-based routers (e.g. Linksys). Most of the discussion centers on difficulties that can arise when using a Wiggler-style cable with the Linksys de-brick utility, but the cable information is applicable to Edimax (ADM5120) devices as well.
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There is a page at the OpenWrt Wiki that discusses [http://wiki.openwrt.org/OpenWrtDocs/Customizing/Hardware/JTAG_Cable JTAG cables].  Specifically, how one Wiggler-style buffered cable can be used for both ADM5120-based routers (e.g. Edimax) and Broadcom-based routers (e.g. Linksys). Most of the discussion centers on difficulties that can arise when using a Wiggler-style cable with the Linksys de-brick utility, but the cable information is applicable to Edimax (ADM5120) devices as well.
  
 
== EJTAG software ==
 
== EJTAG software ==
  
Macraigor [http://www.macraigor.com/ocd_cmd.htm OCD Commander] is a simple JTAG debugger with MIPS support, [http://www.macraigor.com/flash_prog.htm OCD Flash programmer] DEMO version. Requires [http://www.macraigor.com/wiggler.htm Wiggler] probe (Wiggler [http://vlad.org.ua/adm5120/media/adm5120/wiggler.gif clone]).
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Macraigor [http://www.macraigor.com/ocd_cmd.htm OCD Commander] is a simple JTAG debugger with MIPS support, [http://www.macraigor.com/flash_prog.htm OCD Flash programmer] DEMO version. Requires [http://www.macraigor.com/wiggler.htm Wiggler] probe or clone.
  
 
* http://www.baycom.org/~tom/ejtag/  
 
* http://www.baycom.org/~tom/ejtag/  
 
* http://gdbmipsejtag.sourceforge.net/  
 
* http://gdbmipsejtag.sourceforge.net/  
 
* http://www.totalembedded.com/open_source/jtag/mips32_ejtag.php
 
* http://www.totalembedded.com/open_source/jtag/mips32_ejtag.php
* Discussion http://wiki.openwrt.org/zt8qmwz
 
 
* Successful debrick experience http://midge.vlad.org.ua/forum/viewtopic.php?t=121
 
* Successful debrick experience http://midge.vlad.org.ua/forum/viewtopic.php?t=121
  

Revision as of 19:42, 7 July 2006

(E)JTAG in general

Most of modern MIPS SOCs support JTAG (IEEE 1149.1). The MIPS EJTAG is a proprietary extension which utilizes widely used IEEE JTAG pins for debug functions. EJTAG provides: run control, single-step execution, breakpoints on both data and instructions, real-time trace (optional) and direct memory access.

The EJTAG prior v2.6 was not documented, however many SOCs still use it. The v2.6 is fully documented and available on the MIPS site (free registration required). The IMPCODE register contains EJTAGver field, so software should read it to distinguish EJTAG version.

MIPS EJTAG has two modes, one is "DMA" mode where the JTAG can cause CPU bus cycles directly, the other "PrAcc" is where the JTAG interface is used to respond to CPU memory accesses in a special range of memory (DMSEG, 0xFF200000) and you have to write little bits of MIPS code to do what you want and emulate that memory on the host side. All systems support PrAcc mode by nature. The DMA mode is optional and not as widely supported as the normal mode. The presence of DMA mode is noted in the IMPCODE register.

JTAG header

EJTAG utilizes 5-pin interface defined in IEEE 1149.1 JTAG specification for off-chip communications. These signals (TDI, TDO, TMS, TCK and nTRST) forms a Test Access Port (TAP). EJTAG 2.6 defines a 14-pin header (mechanical connector) to attach a JTAG probe.

nTRST  1  2 GND
TDI    3  4 GND
TDO    5  6 GND
TMS    7  8 GND
TCK    9 10 GND
nSRST 11 12 -key
DINT  13 14 VCC

DINT pin is used to raise Debug Interrupt. Many chips has no this pin.

nTRST is a "TAP Reset" signal and it's active level is "0" (the first "n" indicates negative logic). nSRST is optional. This signal resets TAP controller independently from the CPU logic. To conform to MIPS EJTAG specifications this pin should be pulled to the ground via resistor ~1KOhm to keep TAP in reset state w/o probe attached. If probe does not control this pin, you need just to feed logical "1" to nTRST pin or pull this to the +VCC via ~300Ohm resistor.

nSRST is a "system reset" signal and acts like conventional "Reset' button.

(E)JTAG Cables

There is a page at the OpenWrt Wiki that discusses JTAG cables. Specifically, how one Wiggler-style buffered cable can be used for both ADM5120-based routers (e.g. Edimax) and Broadcom-based routers (e.g. Linksys). Most of the discussion centers on difficulties that can arise when using a Wiggler-style cable with the Linksys de-brick utility, but the cable information is applicable to Edimax (ADM5120) devices as well.

EJTAG software

Macraigor OCD Commander is a simple JTAG debugger with MIPS support, OCD Flash programmer DEMO version. Requires Wiggler probe or clone.

In general, the state of EJTAG software is pretty bad. The openwince jtag software can be used to re-flash, but that project is a shambles. If you dig around enough through the patches and discussions there you can find enough to make it work.

Unfortunately, openwince jtag can't identify this processor.

jtag> cable ppdev /dev/parport0 WIGGLER
Initializing Macraigor Wiggler JTAG Cable on ppdev port /dev/parport0
jtag> detect
IR length: 5
Chain length: 1
Device Id: 00000000000000000000000000000001
  Unknown manufacturer!
chain.c(110) Part 0 without active instruction
chain.c(133) Part 0 without active instruction
chain.c(110) Part 0 without active instruction

It seems, it's a real ID for this processor, other JTAG ulilities (i.e. detect subrotine from the wrt54g-debrick) returns the same value...

IMPCODE identification works:

jtag> instruction length 5
jtag> register IMP 32
jtag> instruction IMPCODE 00011 IMP
jtag> instruction IMPCODE
jtag> shift ir
jtag> shift dr
jtag> dr
01000001010000000100000000000000

Decode:

31:29 EJTAGver 010 Version 2.6
   28 R4k/R3k    0 R4k
   24 DINTsup    1 supported
22:21 ASIDsize  10 8-bit ASID
   16 MIPS16e    0 not supported
   14 NoDMA      1 No EJTAG DMA support
    0 MIPS32/64  0 MIPS32

EJTAG CONTROL register:

jtag> instruction length 5
jtag> register ECR 32
jtag> instruction CONTROL 01010 ECR
jtag> instruction CONTROL
jtag> shift ir
jtag> shift dr
jtag> dr
10000000011000000000000000000000

CPU Reset via PrRst bit in the CONTROL EJTAG register works.


External links

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