Instruction Set Architecture
ISA is the abbreviation for Instruction Set Architecture. MIPS processors are being made since 1988. Over time several enhancements of the architecture were made. Of MIPS I, MIPS II, MIPS III, MIPS IV and MIPS V each was a superset of it's predecessors. When MIPS was spun out of SGI again in 1998 and refocused on the embedded market this superset property was found to be a problem and the architecture definition was changed to define a 32-bit MIPS32 and a 64-bit MIPS64 architecture. Frequently the terms MIPS32 and MIPS64 are meant to indicate some generic 32-bit rsp. 64-bit MIPS processor, however.
MIPS II was introduced by the R6000. It adds load linked, store conditional and branch likely instructions. The FPU's instruction set was improved by support of 64-bit loads and stores which half the number of instructions need to load or store a double precission floating point register on MIPS I.
MIPS III was introduced 1992 in the R4000. It adds 64-bit registers and integer instructions and a square root FP instruction.
MIPS IV adds conditional moves and an inverse square root FPU instruction. The R8000 was the first to implement the MIPS IV instruction set.
MIPS V was specified in 1994 by SGI but never actually implemented by any processor. MIPS64 is a superset of MIPS V
MIPS32 is the 32-bit subset of MIPS64.
MIPS32 V2.0 and MIPS64 V2.0
Application Specific Extensions (ASE)
The MIPS instruction set is by far to complex to be covered on this page. The freely available CPU specs are not an easy reading for a first time MIPS'er either so here a literature recommendation:
MIPS RISC Architecture
by author Gerry Kane, publisher Prentice Hall, ISBN 0-13-584293-X / ISBN 013584749-4. This book issued in 1998 is the classic book on MIPS literature. Well written but covering the R3000 and the R3000 only and out of print since ages. The second issue has ISBN 0135904722 and extends on the R6000 and R4000 processors but leaves out alot of details.
See MIPS Run
by author Dominic Sweetman, publisher Morgan Kaufmann, ISBN 1-55860-410-3
This is intended as a pretty comprehensive guide to programming MIPS, wherever it's different from programming any other 32-bit CPU. It's the first time anyone has tried to write a readable, and comprehensive, explanation and account of the wide range of MIPS CPUs available. It should be very helpful for anyone programming MIPS who isn't insulated by someone else's operating system. Also, the author is a free-unix enthusiast who subscribes to the Linux/MIPS mailing list!
John Hennessey, father of the MIPS architecture, was kind enough to write in the foreword: "... this book is the best combination of completeness and readability of any book on the MIPS architecture ...";
It includes some context about RISC CPUs, a description of the architecture and instruction set, including the "co-processor 0" instructions used for CPU control; sections on caches, exceptions, memory management, and floating point. There's a detailed assembly language guide, some stuff about porting, and some fairly heavy-duty software examples.
It's 512 pages and costs around $50 in the US, 34Â£ in the UK.
The MIPS Programmer's Handbook
Authors Farquhar and Bunce, Publisher Morgan Kaufmann, ISBN 1-55860-297-6.
A readable introduction to the practice of programming MIPS at the low level, by the author of PMON. Strengths: lots of examples; weakness: leaves out some big pieces of the architecture (such as memory management, floating point and advanced caches) because they didn't feature in the LSI ``embedded products this book was meant to partner.