Instruction Set Architecture - Revision history

Eigma: Fix link to ASE specs

2012-09-23T08:11:38Z

Fix link to ASE specs

Ralf at 12:07, 24 August 2012

2012-08-24T12:07:17Z

Ralf: Add diagram about MIPS ISAs.

2011-04-07T14:22:54Z

Add diagram about MIPS ISAs.

ISC PB: grammar

2010-08-02T21:05:43Z

grammar

ISC PB: punctuation

2010-08-02T21:04:59Z

punctuation

ISC PB: grammar

2010-08-02T21:03:06Z

grammar

ISC PB: grammar

2010-08-02T21:02:39Z

grammar

ISC PB: Punctuation

2010-08-02T21:01:59Z

Punctuation

Harishnair: /* ISA Levels */

2009-11-16T14:05:54Z

‎ISA Levels

Harishnair: /* ISA Levels */

2009-11-16T06:52:12Z

‎ISA Levels

@@ Line 53: / Line 53: @@
 * [[Books#See_MIPS_Run|See MIPS Run]]
 * [[Books#The_MIPS_Programmer's_Handbook|The MIPS Programmer's Handbook]]
-* [http://www.mips.com/content/Documentation/MIPSDocumentation/ProcessorArchitecture/doclibrary Official documents on the MIPS16, MIPS32, MIPS64 and extensions at mips.com]
+* [http://www.mips.com/products/architectures/mips-dsp-ase/#specifications Official documents on the MIPS16, MIPS32, MIPS64 and extensions at mips.com]

@@ Line 19: / Line 19: @@
 == MIPS32 ==
-MIPS32 is the 32-bit subset of MIPS64.
+MIPS32 is the 32-bit subset of MIPS64.  The current version is MIPS32 Release 3.  Most MIPS32 cores shipping today implement Release 2 of the architecture.
 == MIPS64 ==
-MIPS64 is a superset of the MIPS V.
+MIPS64 is a superset of the MIPS V.  The current version is MIPS32 Release 3.  Most current production MIPS64 cores implement Release 1 of the MIPS64 architecture but a few also implement Release 2.
 == MIPS32 V2.0 and MIPS64 V2.0 ==

← Older revision		Revision as of 14:22, 7 April 2011
Line 1:		Line 1:
	== ISA Levels ==		== ISA Levels ==
		+	[[File:Mips-isas.svg\|200px\|thumb\|right\|Relation of MIPS ISAs]]
	ISA is the abbreviation for ''Instruction Set Architecture''. MIPS processors have been in production since 1988. Over time several enhancements of the architecture were made. The different revisions which have been introduced are MIPS I, MIPS II, MIPS III, MIPS IV and MIPS V. Each revision is a superset of its predecessors. When MIPS was spun out of SGI again in 1998, they refocused on the embedded market. At that time, this superset property was found to be a problem, and the architecture definition was changed to define a 32-bit MIPS32 and a 64-bit MIPS64 architecture. Frequently the terms MIPS32 and MIPS64 are meant to indicate some generic 32-bit and 64-bit MIPS processor, respectively.		ISA is the abbreviation for ''Instruction Set Architecture''. MIPS processors have been in production since 1988. Over time several enhancements of the architecture were made. The different revisions which have been introduced are MIPS I, MIPS II, MIPS III, MIPS IV and MIPS V. Each revision is a superset of its predecessors. When MIPS was spun out of SGI again in 1998, they refocused on the embedded market. At that time, this superset property was found to be a problem, and the architecture definition was changed to define a 32-bit MIPS32 and a 64-bit MIPS64 architecture. Frequently the terms MIPS32 and MIPS64 are meant to indicate some generic 32-bit and 64-bit MIPS processor, respectively.

@@ Line 48: / Line 48: @@
 == Books ==
-The MIPS instruction set is by far to complex to be covered on this page. The freely available CPU specs are not an easy reading for a first time MIPS'er either. So here are some literature recommendations in no particular order.
+The MIPS instruction set is by far too complex to be covered on this page. The freely available CPU specs are not an easy reading for a first time MIPS'er either. So here are some literature recommendations in no particular order:
 * [[Books#MIPS_RISC_Architecture|MIPS RISC Architecture]]
 * [[Books#See_MIPS_Run|See MIPS Run]]
 * [[Books#The_MIPS_Programmer's_Handbook|The MIPS Programmer's Handbook]]
 * [http://www.mips.com/content/Documentation/MIPSDocumentation/ProcessorArchitecture/doclibrary Official documents on the MIPS16, MIPS32, MIPS64 and extensions at mips.com]

@@ Line 31: / Line 31: @@
 Unlike the bulk of the MIPS architecture, it's a fairly irregular set of operations, many chosen for its particular relevance to some key algorithm.
-It's main novel features (vs original MIPS32):
+Its main novel features (vs original MIPS32):
 * Saturating arithmetic (when a calculation overflows, deliver the representable number closest to the non-overflowed answer).

@@ Line 6: / Line 6: @@
 == MIPS II ==
-MIPS II was introduced by the [[R6000]].  It adds load linked, store conditional and branch likely instructions.  The FPU's instruction set was improved by support of 64-bit loads and stores which halved the number of instructions needed to load or store a double precision [[floating point]] register on MIPS I.
+MIPS II was introduced by the [[R6000]].  It adds load linked, store conditional and branch likely instructions.  The FPU's instruction set was improved by support of 64-bit loads and stores which halved the number of instructions needed to load or store a double precision [[floating point]] register when compared to MIPS I.
 == MIPS III ==

@@ Line 1: / Line 1: @@
 == ISA Levels ==
-ISA is the abbreviation for ''Instruction Set Architecture''.  MIPS processors have been in production since 1988.  Over time several enhancements of the architecture were made.  The different revisions which have been introduced are MIPS I, MIPS II, MIPS III, MIPS IV and MIPS V. Each revision is a superset of it's predecessors.  When MIPS was spun out of SGI again in 1998, they refocused on the embedded market. At that time, this superset property was found to be a problem, and the architecture definition was changed to define a 32-bit MIPS32 and a 64-bit MIPS64 architecture.  Frequently the terms MIPS32 and MIPS64 are meant to indicate some generic 32-bit and 64-bit MIPS processor, respectively.
+ISA is the abbreviation for ''Instruction Set Architecture''.  MIPS processors have been in production since 1988.  Over time several enhancements of the architecture were made.  The different revisions which have been introduced are MIPS I, MIPS II, MIPS III, MIPS IV and MIPS V. Each revision is a superset of its predecessors.  When MIPS was spun out of SGI again in 1998, they refocused on the embedded market. At that time, this superset property was found to be a problem, and the architecture definition was changed to define a 32-bit MIPS32 and a 64-bit MIPS64 architecture.  Frequently the terms MIPS32 and MIPS64 are meant to indicate some generic 32-bit and 64-bit MIPS processor, respectively.
 == MIPS I ==