What is the HEART?
The HEART can be accessed in two ways from the processor. The first one is through the PIU (Programmed I/O Unit) at 0xFF0000 in processor physical address space. The other one is at widget 8 in XIO address space. The only one way available to other XIO devices is through the widget interface, so the Interrupt Status Set register is mapped there at address 0x80.
The HEART contains a SDRAM memory controller with ECC. ECC errors are signaled to the CPUs by interrupts.
The XIO bridge is one of the main functions of the HEART. There are three access windows defined for each XIO widget number. There is a window at 0x10000000+ W*0x1000000 for widget number W, a window at 0x800000000+W*0x80000000 and a window at 0x1000000000+W*0x1000000000.
Note that XIO accesses are deeply pipelined by default. Due to that fact, writing to any XIO widget may not have any effect for several hundred cycles. To guarantee finalization of all posted writes it is required to read the widget flush register.
The XIO bridge in HEART provides also some Flow Control features for two channels. They allow to schedule a hiwater IRQ for any given XIO register address. If the register is an input to a FIFO, as is the case with the IMPACT graphics board, exceeding a prescribed number of writes to this register would cause a FIFO hiwater condition. As you already know, the XIO writes are posted and not immediately executed. Catching the hiwater condition in the HEART and not in the card allows to trap it in a more reliable way.
The HEART interrupt controller is visible from the PIU as a set of registers: interrupt mask registers for all processors (IMR[0:3]), an interrupt status register (ISR) and ISR clear and set registers that allow atomic manipulation of the ISR.
The XIO side consists of a single register 0x80 that can accept either an atomic ISR bit set command or an atomic ISR bit clear command. These commands cause asserting and deasserting IP[7:2] bits in the CPUs whose IMRs contain the bit in question.
A small part of the HEART is a programmable interval timer, consisting of 24-bit COUNT and COMPARE registers. The IRQ can be delivered only to the IP6 bit, which is the highest-priority CPU interrupt except internal CPU timer and HEART error IRQs. The timer counts at 12.5 MHz, every 8th internal HEART cycle (1/4th of the XIO frequency).
The HEART controls also the NICs associated with processor modules. It features a standard SGI issue MicroLAN controller.