BCM1250 - Revision history

Alec v: link

2007-10-02T08:24:39Z

link

Headless at 19:14, 17 June 2006

2006-06-17T19:14:09Z

Headless at 19:11, 17 June 2006

2006-06-17T19:11:12Z

Headless at 19:10, 17 June 2006

2006-06-17T19:10:32Z

Ralf: Change SoC to SOC

2006-05-16T11:37:53Z

Change SoC to SOC

Ralf: Change SoC link to SOC

2006-05-16T11:33:44Z

Change SoC link to SOC

Ralf: Clarify the BCM1250 has MIPS64 cores.

2006-05-15T16:07:39Z

Clarify the BCM1250 has MIPS64 cores.

Ralf: Add to SOC category

2006-05-15T12:51:45Z

Add to SOC category

Ralf: Make HT a link

2006-03-17T11:38:55Z

Make HT a link

Alec v: user manual link

2005-05-25T14:30:20Z

user manual link

@@ Line 1: / Line 1: @@
 '''BCM1250''' that integrates two [[MIPS64]] [[SB1]] CPU cores, each scalable to 600 MHz - 1 GHz, a large cache memory, and integrated I/O into a [[SOC]]. The BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 GB of memory. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for [[HyperTransport]], a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug features.
-[http://sibyte.broadcom.com/public/resources/#um BCM1250 and BCM1125H User Manual]
+[http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors Broadcom Communications Processors]
 == Evaluation platforms ==

@@ Line 5: / Line 5: @@
 == Evaluation platforms ==
 === SWARM ===
-An evaluation board platform, called [[Swarm|BCM91250A]], uses of all the interfaces on the BCM1250, and can be used with any ATX 2.0 compliant case and power supply. Off-the-shelf peripherals including PCI graphics adapters, USB keyboards and mice, and ATA hard disks can be added. The board supports VxWorks 5.4, Linux 2.4 running in 32-bit mode with SMP support, and NetBSD 1.5 running in 32-bit mode.
+An evaluation board platform, called [[SWARM|BCM91250A]], uses of all the interfaces on the BCM1250, and can be used with any ATX 2.0 compliant case and power supply. Off-the-shelf peripherals including PCI graphics adapters, USB keyboards and mice, and ATA hard disks can be added. The board supports VxWorks 5.4, Linux 2.4 running in 32-bit mode with SMP support, and NetBSD 1.5 running in 32-bit mode.
 === Sentosa ===

@@ Line 5: / Line 5: @@
 == Evaluation platforms ==
 === SWARM ===
-An evaluation board platform, called BCM91250A, uses of all the interfaces on the BCM1250, and can be used with any ATX 2.0 compliant case and power supply. Off-the-shelf peripherals including PCI graphics adapters, USB keyboards and mice, and ATA hard disks can be added. The board supports VxWorks 5.4, Linux 2.4 running in 32-bit mode with SMP support, and NetBSD 1.5 running in 32-bit mode.
+An evaluation board platform, called [[Swarm|BCM91250A]], uses of all the interfaces on the BCM1250, and can be used with any ATX 2.0 compliant case and power supply. Off-the-shelf peripherals including PCI graphics adapters, USB keyboards and mice, and ATA hard disks can be added. The board supports VxWorks 5.4, Linux 2.4 running in 32-bit mode with SMP support, and NetBSD 1.5 running in 32-bit mode.
 === Sentosa ===

@@ Line 4: / Line 4: @@
 == Evaluation platforms ==
-=== Swarm ===
+=== SWARM ===
-An evaluation board platform, called the [[Swarm|BCM91250A]], uses of all the interfaces on the BCM1250, and can be used with any ATX 2.0 compliant case and power supply. Off-the-shelf peripherals including PCI graphics adapters, USB keyboards and mice, and ATA hard disks can be added. The board supports VxWorks 5.4, Linux 2.4 running in 32-bit mode with SMP support, and NetBSD 1.5 running in 32-bit mode.
+An evaluation board platform, called BCM91250A, uses of all the interfaces on the BCM1250, and can be used with any ATX 2.0 compliant case and power supply. Off-the-shelf peripherals including PCI graphics adapters, USB keyboards and mice, and ATA hard disks can be added. The board supports VxWorks 5.4, Linux 2.4 running in 32-bit mode with SMP support, and NetBSD 1.5 running in 32-bit mode.
 === Sentosa ===
-Sentosa is architecturally somwhat similar to the Swarm due to the use of the same SOC but a full length [[WikiPedia:Peripheral_Component_Interconnect|PCI]] with memory soldered onto the board itself.  It supports the same software.
+Sentosa (BCM91250E) is architecturally somewhat similar to the SWARM due to the use of the same SOC but a full length [[WikiPedia:Peripheral_Component_Interconnect|PCI]] with memory soldered onto the board itself.  It supports the same software.
 [[Category:SOC]]

@@ Line 8: / Line 8: @@
 === Sentosa ===
-Sentosa is architecturally somwhat similar to the Swarm due to the use of the same [[SoC]] but a full length [[WikiPedia:Peripheral_Component_Interconnect|PCI]] with memory soldered onto the board itself.  It supports the same software.
+Sentosa is architecturally somwhat similar to the Swarm due to the use of the same SOC but a full length [[WikiPedia:Peripheral_Component_Interconnect|PCI]] with memory soldered onto the board itself.  It supports the same software.
 [[Category:SOC]]

← Older revision		Revision as of 11:33, 16 May 2006
Line 1:		Line 1:
−	'''BCM1250''' that integrates two [[MIPS64]] [[SB1]] CPU cores, each scalable to 600 MHz - 1 GHz, a large cache memory, and integrated I/O into a [[~~SoC~~]]. The BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 GB of memory. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for [[HyperTransport]], a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug features.	+	'''BCM1250''' that integrates two [[MIPS64]] [[SB1]] CPU cores, each scalable to 600 MHz - 1 GHz, a large cache memory, and integrated I/O into a [[SOC]]. The BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 GB of memory. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for [[HyperTransport]], a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug features.

	[http://sibyte.broadcom.com/public/resources/#um BCM1250 and BCM1125H User Manual]		[http://sibyte.broadcom.com/public/resources/#um BCM1250 and BCM1125H User Manual]

← Older revision		Revision as of 16:07, 15 May 2006
Line 1:		Line 1:
−	'''BCM1250''' that integrates two ~~64-bit MIPS~~ CPU cores, each scalable to 600 MHz - 1 GHz, a large cache memory, and integrated I/O into a [[SoC]]. The BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 GB of memory. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for [[HyperTransport]], a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug features.	+	'''BCM1250''' that integrates two [[MIPS64]] [[SB1]] CPU cores, each scalable to 600 MHz - 1 GHz, a large cache memory, and integrated I/O into a [[SoC]]. The BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 GB of memory. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for [[HyperTransport]], a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug features.

	[http://sibyte.broadcom.com/public/resources/#um BCM1250 and BCM1125H User Manual]		[http://sibyte.broadcom.com/public/resources/#um BCM1250 and BCM1125H User Manual]

← Older revision		Revision as of 12:51, 15 May 2006
Line 9:		Line 9:
	=== Sentosa ===		=== Sentosa ===
	Sentosa is architecturally somwhat similar to the Swarm due to the use of the same [[SoC]] but a full length [[WikiPedia:Peripheral_Component_Interconnect\|PCI]] with memory soldered onto the board itself. It supports the same software.		Sentosa is architecturally somwhat similar to the Swarm due to the use of the same [[SoC]] but a full length [[WikiPedia:Peripheral_Component_Interconnect\|PCI]] with memory soldered onto the board itself. It supports the same software.
		+
		+	[[Category:SOC]]

← Older revision		Revision as of 11:38, 17 March 2006
Line 1:		Line 1:
−	'''BCM1250''' that integrates two 64-bit MIPS CPU cores, each scalable to 600 MHz - 1 GHz, a large cache memory, and integrated I/O into a [[SoC]]. The BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 GB of memory. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for HyperTransport, a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug features.	+	'''BCM1250''' that integrates two 64-bit MIPS CPU cores, each scalable to 600 MHz - 1 GHz, a large cache memory, and integrated I/O into a [[SoC]]. The BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 GB of memory. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for [[HyperTransport]], a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug features.

	[http://sibyte.broadcom.com/public/resources/#um BCM1250 and BCM1125H User Manual]		[http://sibyte.broadcom.com/public/resources/#um BCM1250 and BCM1125H User Manual]

← Older revision		Revision as of 14:30, 25 May 2005
Line 1:		Line 1:
	'''BCM1250''' that integrates two 64-bit MIPS CPU cores, each scalable to 600 MHz - 1 GHz, a large cache memory, and integrated I/O into a [[SoC]]. The BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 GB of memory. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for HyperTransport, a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug features.		'''BCM1250''' that integrates two 64-bit MIPS CPU cores, each scalable to 600 MHz - 1 GHz, a large cache memory, and integrated I/O into a [[SoC]]. The BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 GB of memory. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for HyperTransport, a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug features.
		+
		+	[http://sibyte.broadcom.com/public/resources/#um BCM1250 and BCM1125H User Manual]

	== Evaluation platforms ==		== Evaluation platforms ==