Difference between revisions of "BCM1250"

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'''BCM1250''' that integrates two [[MIPS64]] [[SB1]] CPU cores, each scalable to 600 MHz - 1 GHz, a large cache memory, and integrated I/O into a [[SOC]]. The BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 GB of memory. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for [[HyperTransport]], a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug features.
 
'''BCM1250''' that integrates two [[MIPS64]] [[SB1]] CPU cores, each scalable to 600 MHz - 1 GHz, a large cache memory, and integrated I/O into a [[SOC]]. The BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 GB of memory. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for [[HyperTransport]], a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug features.
  
[http://sibyte.broadcom.com/public/resources/#um BCM1250 and BCM1125H User Manual]
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[http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors Broadcom Communications Processors]
  
 
== Evaluation platforms ==
 
== Evaluation platforms ==

Revision as of 08:24, 2 October 2007

BCM1250 that integrates two MIPS64 SB1 CPU cores, each scalable to 600 MHz - 1 GHz, a large cache memory, and integrated I/O into a SOC. The BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 GB of memory. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for HyperTransport, a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug features.

Broadcom Communications Processors

Evaluation platforms

SWARM

An evaluation board platform, called BCM91250A, uses of all the interfaces on the BCM1250, and can be used with any ATX 2.0 compliant case and power supply. Off-the-shelf peripherals including PCI graphics adapters, USB keyboards and mice, and ATA hard disks can be added. The board supports VxWorks 5.4, Linux 2.4 running in 32-bit mode with SMP support, and NetBSD 1.5 running in 32-bit mode.

Sentosa

Sentosa (BCM91250E) is architecturally somewhat similar to the SWARM due to the use of the same SOC but a full length PCI with memory soldered onto the board itself. It supports the same software.