Aptiv - Revision history

Sjhill: /* See also */

2012-09-06T17:55:27Z

‎See also

Ralf at 12:22, 30 August 2012

2012-08-30T12:22:06Z

Ralf at 12:03, 24 August 2012

2012-08-24T12:03:42Z

Ralf: Created page with "MIPS announced the '''Aptiv''' product line on May 10, 2012. The Aptiv series are MIPS32 Rev 3 is derived of the 74K and consists of three (+1) family members: * ..."

2012-08-24T12:02:43Z

Created page with "MIPS announced the '''Aptiv''' product line on May 10, 2012. The Aptiv series are MIPS32 Rev 3 is derived of the 74K and consists of three (+1) family members: * ..."

New page

MIPS announced the '''Aptiv''' product line on May 10, [[2012]]. The Aptiv series are [[MIPS32 Rev 3]] is derived of the [[74K]] and consists of three (+1) family members:
* microAptiv This core is marketed as a highend synthesizable microcontroller. It features mipsMIPS code compression, the [[DSP ASE Rev 2]]. A standard MIPS TLB and a simpler segmented MMU are synthesizable options of the core. Linux ''requires'' the TLB to work! There is no FPU option for the microAptiv.
* interAptiv I/O coherence manager (you want it), Global Interrupt Controller ([[GIC]]), FPU
* proAptiv I/O coherence manager (you want it), Global Interrupt Controller ([[GIC]]), FPU, MIPS16e, multi-core
* radioAptiv featuring a [http://www.youtube.com/watch?v=8trsDPpAI5E nanoEGG™] for powersupply. First samples can be found walking around in the seas around Japan.

== Linux support ==
No patches for Aptiva support have been submitted yet. Since the core largely is an advanced implementation of already existing technologies Aptiva support is expected to be a relatively simple task.

== Notes ==
The list of Aptiv family members may be inaccurate.

== See also ==
* http://www.youtube.com/watch?v=3EHVM17RJcg MIPS propaganda video for the Aptiv codes

← Older revision		Revision as of 17:55, 6 September 2012
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	== See also ==		== See also ==
−	* http://www.youtube.com/watch?v=3EHVM17RJcg MIPS propaganda video for the Aptiv ~~codes~~	+	* http://www.youtube.com/watch?v=3EHVM17RJcg MIPS propaganda video for the Aptiv cores.

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-MIPS announced the '''Aptiv''' product line on May 10, [[2012]].  The Aptiv series are [[MIPS32 Rev 3]] is derived of the [[74K]] and consists of three (+1) family members:
+MIPS announced the '''Aptiv''' product line on May 10, [[2012]].  The Aptiv family is sometimes also refered to under its codename Impresa.  The Aptiv series are [[MIPS32 Rev 3]] is derived of the [[74K]] and consists of three (+1) family members:
 * microAptiv This core is marketed as a highend synthesizable microcontroller.  It features mipsMIPS code compression, the [[DSP ASE Rev 2]].  A standard MIPS TLB and a simpler segmented MMU are synthesizable options of the core.  Linux ''requires'' the TLB to work!  There is no FPU option for the microAptiv.
 * interAptiv I/O coherence manager (you want it), Global Interrupt Controller ([[GIC]]), FPU

@@ Line 6: / Line 6: @@
 == Linux support ==
-No patches for Aptiva support have been submitted yet.  Since the core largely is an advanced implementation of already existing technologies Aptiva support is expected to be a relatively simple task.
+No patches for Aptiv support have been submitted yet.  Since the core largely is an advanced implementation of already existing technologies Aptiv support is expected to be a relatively simple task.
 == Notes ==