Difference between revisions of "Aptiv"

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(Created page with "MIPS announced the '''Aptiv''' product line on May 10, 2012. The Aptiv series are MIPS32 Rev 3 is derived of the 74K and consists of three (+1) family members: * ...")
 
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MIPS announced the '''Aptiv''' product line on May 10, [[2012]].  The Aptiv series are [[MIPS32 Rev 3]] is derived of the [[74K]] and consists of three (+1) family members:
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MIPS announced the [[Aptiv]] product line on May 10, [[2012]].  The Aptiv series are [[MIPS32 Release 3]] and consists of three family members:
* microAptiv This core is marketed as a highend synthesizable microcontroller.  It features mipsMIPS code compression, the [[DSP ASE Rev 2]].  A standard MIPS TLB and a simpler segmented MMU are synthesizable options of the core.  Linux ''requires'' the TLB to work!  There is no FPU option for the microAptiv.
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* interAptiv I/O coherence manager (you want it), Global Interrupt Controller ([[GIC]]), FPU
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* [[proAptiv]]: I/O coherence manager ([[CM]]), Global Interrupt Controller ([[GIC]]), FPU, [[MIPS16|MIPS16e]], multi-core
* proAptiv I/O coherence manager (you want it), Global Interrupt Controller ([[GIC]]), FPU, MIPS16e, multi-core
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* [[interAptiv]]: I/O coherence manager ([[CM]]), Global Interrupt Controller ([[GIC]]), FPU multi-core, multi-thread ([[MT]])
* radioAptiv featuring a [http://www.youtube.com/watch?v=8trsDPpAI5E nanoEGG™] for powersupplyFirst samples can be found walking around in the seas around Japan.
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* [[microAptiv]]: [[microMIPS]], [[DSP ASE Rev 2]].
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** A standard MIPS TLB and a simpler segmented MMU are synthesizable options of the core, giving two variants of core - the MCU (not Linux capable) and the MPU (Linux capable)There is no FPU option for the microAptiv.
  
 
== Linux support ==
 
== Linux support ==
No patches for Aptiva support have been submitted yet.  Since the core largely is an advanced implementation of already existing technologies Aptiva support is expected to be a relatively simple task.
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Patches for Aptiv support are available in the IMG mti branches of the [[LinuxMipsOrg|LMO]] [http://git.linux-mips.org/ git repository], and are in the process of being submitted.
 
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== Notes ==
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The list of Aptiv family members may be inaccurate.
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== See also ==
 
== See also ==
* http://www.youtube.com/watch?v=3EHVM17RJcg MIPS propaganda video for the Aptiv codes
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* http://www.youtube.com/watch?v=3EHVM17RJcg MIPS propaganda video for the Aptiv cores.
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* http://www.imgtec.com/mips/mips-proaptiv.asp IMG proAptiv web page
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* http://git.linux-mips.org/?p=linux-mti.git;a=summary [[LinuxMipsOrg|LMO]] hosted IMG mti git page
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[[category:MIPS32 Release 3]]

Revision as of 23:05, 5 December 2013

MIPS announced the Aptiv product line on May 10, 2012. The Aptiv series are MIPS32 Release 3 and consists of three family members:

  • proAptiv: I/O coherence manager (CM), Global Interrupt Controller (GIC), FPU, MIPS16e, multi-core
  • interAptiv: I/O coherence manager (CM), Global Interrupt Controller (GIC), FPU multi-core, multi-thread (MT)
  • microAptiv: microMIPS, DSP ASE Rev 2.
    • A standard MIPS TLB and a simpler segmented MMU are synthesizable options of the core, giving two variants of core - the MCU (not Linux capable) and the MPU (Linux capable). There is no FPU option for the microAptiv.

Linux support

Patches for Aptiv support are available in the IMG mti branches of the LMO git repository, and are in the process of being submitted.

See also