Difference between revisions of "Aptiv"

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MIPS announced the '''Aptiv''' product line on May 10, [[2012]].  The Aptiv series are [[MIPS32 Rev 3]] and consists of three family members:
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MIPS announced the [[Aptiv]] product line on May 10, [[2012]].  The Aptiv series are [[MIPS32 Release 3]] and consists of three family members:
  
 
* [[proAptiv]]: I/O coherence manager ([[CM]]), Global Interrupt Controller ([[GIC]]), FPU, [[MIPS16|MIPS16e]], multi-core
 
* [[proAptiv]]: I/O coherence manager ([[CM]]), Global Interrupt Controller ([[GIC]]), FPU, [[MIPS16|MIPS16e]], multi-core

Revision as of 22:51, 5 December 2013

MIPS announced the Aptiv product line on May 10, 2012. The Aptiv series are MIPS32 Release 3 and consists of three family members:

  • proAptiv: I/O coherence manager (CM), Global Interrupt Controller (GIC), FPU, MIPS16e, multi-core
  • interAptiv: I/O coherence manager (CM), Global Interrupt Controller (GIC), FPU multi-core, multi-thread (MT)
  • microAptiv: microMIPS, DSP ASE Rev 2.
    • A standard MIPS TLB and a simpler segmented MMU are synthesizable options of the core, giving two variants of core - the MCU (not Linux capable) and the MPU (Linux capable). There is no FPU option for the microAptiv.

Linux support

Patches for Aptiv support are available in the IMG mti branches of the LMO git repository, and are in the process of being submitted.

See also