Difference between revisions of "Aptiv"
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| − | * http://www.youtube.com/watch?v=3EHVM17RJcg MIPS propaganda video for the Aptiv | + | * http://www.youtube.com/watch?v=3EHVM17RJcg MIPS propaganda video for the Aptiv cores. |
Latest revision as of 17:55, 6 September 2012
MIPS announced the Aptiv product line on May 10, 2012. The Aptiv family is sometimes also refered to under its codename Impresa. The Aptiv series are MIPS32 Rev 3 is derived of the 74K and consists of three (+1) family members:
- microAptiv This core is marketed as a highend synthesizable microcontroller. It features mipsMIPS code compression, the DSP ASE Rev 2. A standard MIPS TLB and a simpler segmented MMU are synthesizable options of the core. Linux requires the TLB to work! There is no FPU option for the microAptiv.
- interAptiv I/O coherence manager (you want it), Global Interrupt Controller (GIC), FPU
- proAptiv I/O coherence manager (you want it), Global Interrupt Controller (GIC), FPU, MIPS16e, multi-core
- radioAptiv featuring a nanoEGG™ for powersupply. First samples can be found walking around in the seas around Japan.
[edit] Linux support
No patches for Aptiv support have been submitted yet. Since the core largely is an advanced implementation of already existing technologies Aptiv support is expected to be a relatively simple task.
[edit] Notes
The list of Aptiv family members may be inaccurate.
[edit] See also
- http://www.youtube.com/watch?v=3EHVM17RJcg MIPS propaganda video for the Aptiv cores.
