Difference between revisions of "Alchemy"

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== UART ==
 
== UART ==
By default the [[YAMON]] bootloader only enables the UART's it is using, two at max. For the AU1100 only UART0 and UAR3 are enabled, leaving UART1 non-functional. You can simply edit the reset source file named arch/init/reset_<name of your platform>.c to enable it. Check for the uart_enable register (Offset=0x0100 from the base address) in the databook. After you've enabled it, the Linux kernel driver ''8250_au1x00.c'' will detect it automatically.
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By default the [[YAMON]] bootloader only enables the UART's it is using, two at max. For the AU1100 only UART0 and UAR3 are enabled, leaving UART1 non-functional. You can simply edit the reset source file named arch/init/reset_<name of your platform>.c to enable it. Check for the uart_enable register (Offset=0x0100 from the base address) in the databook. After you've enabled it, the Linux kernel driver ''(8250_au1x00.c)'' will detect it automatically.
  
 
== See also ==
 
== See also ==

Revision as of 12:36, 7 September 2006

This article is a stub. You can help by expanding it

The Alchemy SOC family is based on an Alchemy-proprietary MIPS32 core. The models are called Au1000, Au1100, Au1500, Au1550, and Au1200.

Alchemy Semiconductor has been acquired by AMD in 2002, which recently (summer 2006) sold the Alchemy processor line to Raza Microelectronics, Inc.

Devices based on the AMD Alchemy

UART

By default the YAMON bootloader only enables the UART's it is using, two at max. For the AU1100 only UART0 and UAR3 are enabled, leaving UART1 non-functional. You can simply edit the reset source file named arch/init/reset_<name of your platform>.c to enable it. Check for the uart_enable register (Offset=0x0100 from the base address) in the databook. After you've enabled it, the Linux kernel driver (8250_au1x00.c) will detect it automatically.

See also

External links