Difference between revisions of "APIC"
From LinuxMIPS
(APIC is a NULL-topic on MIPS, yeah!) |
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| − | Advanced Programmable Interrupt Controller (I/O APIC) provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable. | + | Advanced Programmable Interrupt Controller (I/O '''APIC''') provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable. |
| − | == | + | == APIC-free zone == |
| − | * [http://www.intel.com/design/chipsets/datashts/290566.htm Intel® 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC)] | + | The APIC just like it's ancestor is infamous for being a problematic bit of silicon. If fortunately has no relevance for MIPS systems as MIPS systems don't use it - even though it may be physically present in some systems. |
| − | * [http://www.intel.com/design/pentium4/manuals/index_new.htm IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide] (Local APIC | + | |
| + | == See also == | ||
| + | * [http://www.intel.com/design/chipsets/datashts/290566.htm Intel® 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC)] | ||
| + | * [http://www.intel.com/design/pentium4/manuals/index_new.htm IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide] (Local APIC) | ||
Revision as of 14:00, 22 February 2006
Advanced Programmable Interrupt Controller (I/O APIC) provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable.
APIC-free zone
The APIC just like it's ancestor is infamous for being a problematic bit of silicon. If fortunately has no relevance for MIPS systems as MIPS systems don't use it - even though it may be physically present in some systems.
