Difference between revisions of "APIC"

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Advanced Programmable Interrupt Controller (I/O APIC) provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable.
 
Advanced Programmable Interrupt Controller (I/O APIC) provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable.
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== Weblinks ==
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* [http://www.intel.com/design/chipsets/datashts/290566.htm Intel® 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC)] (englisch)
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* [http://www.intel.com/design/pentium4/manuals/index_new.htm IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide] (Local APIC, englisch)
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[[Kategorie:Hardware]]
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[[ca:APIC]]
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[[en:Intel APIC Architecture]]
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[[es:APIC]]
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[[fr:IO-APIC]]
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[[pl:APIC]]

Revision as of 09:16, 21 February 2006

Advanced Programmable Interrupt Controller (I/O APIC) provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable.

Weblinks

Kategorie:Hardware

ca:APIC en:Intel APIC Architecture es:APIC fr:IO-APIC pl:APIC