Difference between revisions of "APIC"
From LinuxMIPS
| Line 1: | Line 1: | ||
Advanced Programmable Interrupt Controller (I/O APIC) provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable. | Advanced Programmable Interrupt Controller (I/O APIC) provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable. | ||
| + | |||
| + | == Weblinks == | ||
| + | * [http://www.intel.com/design/chipsets/datashts/290566.htm Intel® 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC)] (englisch) | ||
| + | * [http://www.intel.com/design/pentium4/manuals/index_new.htm IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide] (Local APIC, englisch) | ||
| + | |||
| + | [[Kategorie:Hardware]] | ||
| + | |||
| + | [[ca:APIC]] | ||
| + | [[en:Intel APIC Architecture]] | ||
| + | [[es:APIC]] | ||
| + | [[fr:IO-APIC]] | ||
| + | [[pl:APIC]] | ||
Revision as of 09:16, 21 February 2006
Advanced Programmable Interrupt Controller (I/O APIC) provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable.
Weblinks
- Intel® 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC) (englisch)
- IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide (Local APIC, englisch)
ca:APIC en:Intel APIC Architecture es:APIC fr:IO-APIC pl:APIC
