Difference between revisions of "APIC"

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Advanced Programmable Interrupt Controller (I/O APIC) provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable.
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Advanced Programmable Interrupt Controller (I/O '''APIC''') provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable.
  
== Weblinks ==
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== APIC-free zone ==
* [http://www.intel.com/design/chipsets/datashts/290566.htm Intel® 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC)] (englisch)
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The APIC just like it's ancestor is infamous for being a problematic bit of silicon. If fortunately has no relevance for MIPS systems as MIPS systems don't use it - even though it may be physically present in some systems.
* [http://www.intel.com/design/pentium4/manuals/index_new.htm IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide] (Local APIC, englisch)
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[[Kategorie:Hardware]]
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== See also ==
 
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* [[Wikipedia:APIC|APIC]] article at Wikipedia.
[[ca:APIC]]
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* [http://www.intel.com/design/chipsets/datashts/290566.htm Intel 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC)]
[[en:Intel APIC Architecture]]
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* [http://www.intel.com/design/pentium4/manuals/index_new.htm IA-32 Intel Architecture Software Developer's Manual Volume 3: System Programming Guide] (Local APIC)
[[es:APIC]]
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[[fr:IO-APIC]]
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[[pl:APIC]]
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Latest revision as of 16:29, 13 August 2012

Advanced Programmable Interrupt Controller (I/O APIC) provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable.

APIC-free zone

The APIC just like it's ancestor is infamous for being a problematic bit of silicon. If fortunately has no relevance for MIPS systems as MIPS systems don't use it - even though it may be physically present in some systems.

See also