Revision as of 17:10, 5 December 2005 by Ralf
The MIPS 4K series is MIPS Technologies low end, synthesizable core implementing the MIPS32 architecture.
- 4Kpâ„¢ core - basic version with iterative multiply and FMT MMU
- 4KmÂ® core - 4Kp core plus fast Multiply/Divide Unit
- 4KcÂ® core - 4Km core plus TLB MMU
The 4Kc CPU supports:
- MIPS32 compatible instruction set
- All MIPS II instructions
- Multiply-Add and Multiply-Sustract instructions (MADD, MADDU, MSUB, MSUBU)
- Targeted Multiply instruction (MUL)
- Zero and One detect instructions (CLZ, CLO)
- Wait Instruction (WAIT)
- Conditional Move instructions (MOVZ, MOVN)
- Prefetch instructions (PREF)
- MIPS32 priveleged resource architecture
- Count/Compare CP0 registers for real-time timer interrupts
- Instruction and Data watch CP0 registers for software breakpoints
- Separate interrupt exeption vector
- Memory Management Unit
- 16 dual-entry MIPS32 style JTLB with variable page sizes
The 4K and 4KE are fully supported.
- Prefetching The use of the pref instruction in Linux.