Difference between revisions of "4K"
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The MIPS '''4K''' series is MIPS Technologies low end, synthesizable core implementing the [[MIPS32]] architecture. | The MIPS '''4K''' series is MIPS Technologies low end, synthesizable core implementing the [[MIPS32]] architecture. | ||
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* 4Km® core - 4Kp core plus fast Multiply/Divide Unit | * 4Km® core - 4Kp core plus fast Multiply/Divide Unit | ||
* 4Kc® core - 4Km core plus TLB MMU | * 4Kc® core - 4Km core plus TLB MMU | ||
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| + | The 4Kc CPU supports: | ||
| + | * [[MIPS32]] compatible instruction set | ||
| + | ** All [[Instruction_Set_Architecture#MIPS_II | MIPS II]] instructions | ||
| + | ** Multiply-Add and Multiply-Sustract instructions (MADD, MADDU, MSUB, MSUBU) | ||
| + | ** Targeted Multiply instruction (MUL) | ||
| + | ** Zero and One detect instructions (CLZ, CLO) | ||
| + | ** Wait Instruction (WAIT) | ||
| + | ** Conditional Move instructions (MOVZ, MOVN) | ||
| + | ** Prefetch instructions (PREF) | ||
| + | * MIPS32 priveleged resource architecture | ||
| + | ** Count/Compare CP0 registers for real-time timer interrupts | ||
| + | ** Instruction and Data watch CP0 registers for software breakpoints | ||
| + | ** Separate interrupt exeption vector | ||
| + | * Memory Management Unit | ||
| + | ** 16 dual-entry MIPS32 style JTLB with variable page sizes | ||
= 4KE = | = 4KE = | ||
Revision as of 08:09, 6 July 2005
The MIPS 4K series is MIPS Technologies low end, synthesizable core implementing the MIPS32 architecture.
- 4Kpâ„¢ core - basic version with iterative multiply and FMT MMU
- 4Km® core - 4Kp core plus fast Multiply/Divide Unit
- 4Kc® core - 4Km core plus TLB MMU
The 4Kc CPU supports:
- MIPS32 compatible instruction set
- All MIPS II instructions
- Multiply-Add and Multiply-Sustract instructions (MADD, MADDU, MSUB, MSUBU)
- Targeted Multiply instruction (MUL)
- Zero and One detect instructions (CLZ, CLO)
- Wait Instruction (WAIT)
- Conditional Move instructions (MOVZ, MOVN)
- Prefetch instructions (PREF)
- MIPS32 priveleged resource architecture
- Count/Compare CP0 registers for real-time timer interrupts
- Instruction and Data watch CP0 registers for software breakpoints
- Separate interrupt exeption vector
- Memory Management Unit
- 16 dual-entry MIPS32 style JTLB with variable page sizes
4KE
Linux support
The 4K and 4KE are fully supported.
