Difference between revisions of "4K"
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The MIPS '''4K''' series is MIPS Technologies's low end [[MIPS32]] synthesizable. | The MIPS '''4K''' series is MIPS Technologies's low end [[MIPS32]] synthesizable. | ||
| − | [http://www.mips.com/ | + | [http://www.mips.com/products/processors/hard-ip-cores/4kc-hard-ip-core/ MIPS32 4Kc Family] |
| − | + | ||
| − | + | ||
* 4Kp core - basic version with iterative multiply and FMT MMU | * 4Kp core - basic version with iterative multiply and FMT MMU | ||
| Line 11: | Line 9: | ||
The 4Kc CPU supports: | The 4Kc CPU supports: | ||
| + | * [[Instruction_Set_Architecture#MIPS32|MIPS32]] compatible instruction set and priveleged resource architecture | ||
** Instruction and Data watch CP0 registers for software breakpoints | ** Instruction and Data watch CP0 registers for software breakpoints | ||
** Separate interrupt exeption vector | ** Separate interrupt exeption vector | ||
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= 4KE = | = 4KE = | ||
| − | [http://www.mips.com/ | + | [http://www.mips.com/products/processors/hard-ip-cores/4kec-hard-ip-cores/ MIPS32 4KEc Family] |
== Linux support == | == Linux support == | ||
Latest revision as of 16:19, 3 January 2009
The MIPS 4K series is MIPS Technologies's low end MIPS32 synthesizable.
- 4Kp core - basic version with iterative multiply and FMT MMU
- 4Km core - 4Kp core plus fast Multiply/Divide Unit
- 4Kc core - 4Km core plus TLB MMU
The 4Kc CPU supports:
- MIPS32 compatible instruction set and priveleged resource architecture
- Instruction and Data watch CP0 registers for software breakpoints
- Separate interrupt exeption vector
- Memory Management Unit
- 16 dual-entry MIPS32 style TLB with variable page sizes
[edit] 4KE
[edit] Linux support
The 4K and 4KE are fully supported.
[edit] See also
- Prefetching The use of the pref instruction in Linux.
