riscy
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Re: 21066 evaluation board summary

To: pat@wesson.it.com.au, riscy@sunsite.unc.edu
Subject: Re: 21066 evaluation board summary
From: Drew Eckhardt <drew@kinglear.cs.Colorado.EDU>
Date: Wed, 02 Feb 1994 18:22:02 -0700
In-reply-to: Your message of "Wed, 02 Feb 1994 17:27:26 EST." <m0pRbXC-0004oUC@wesson>
--------

    The other point I'm a little worried about is the fact that these chips
    want ECC on their memory. If it's a 32 bit memory + 8 bit ECC, doesn't
    that mean we need "special" SIMMs, rather than the more common 36 bit
    PC SIMMs? Perhaps I'm wrong here also and there is extra ECC memory
    configured into the system (not necessarily in the SIMMs)?

1.  Memory is 64 bits wide

2.  With 64 bit wide memory, you need 8 bits for SECDED
        (Single bit Error Correction, Double bit Error Dedection)

3.  64 data bits + 8 ECC bits = 72 bits = 2 x 36 bit memories

No problem - it's no more expensive in terms of memory than one 
parity bit per byte, and will correct one bit errors instead of 
halting.
    
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