By writing PALcode that approximates the MM of the 386, a porting
effort could be made a lot easier. We would also be able to use
Drew's PCI scsi driver, with few or no changes, which would be a big
win. A RISC chip with 386-like MM and all the major devices already
supported in Linux/86 would make for relatively easy porting, other
than places where going from 32 to 64 bits causes problems, which
shouldn't be too many places. Hopefully, GCC will have improved code
generation for the ALPHA by that time...
Where as many CISC chips (ie, the i86 and M68k series) provide a user
interface to the VM hardware using a page-table abstraction, most
RISC chips I've seen (ie, the R4000 series) don't waste space on
microcode and force the user to handle TLB misses in software.
I find it unlikely that the ALPHA will be any different, in
which case PAL code will be unecessary and the TLB exception handler
can use any sort of page table we care to use - like the i386 page
NCR53c810 support - if the chips are running little-endian, there
shouldn't be any problems.