riscy
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RE: L2 Caching and SIMMs format

To: riscy@sunsite.unc.edu
Subject: RE: L2 Caching and SIMMs format
From: vince@cardiothoracic.ucsf.edu
Date: Sat, 20 Nov 1993 09:42:20 EST
Daniel,
        Maybe you missed a post I made about a week or so ago. A company called
ramtron makes 72 pin simms with the sram cache integrated into the simms. The 
sisimms have some cahche cohernecy function built in, but for best use, a new 
simmcontroller module is needed.  These simms have quite a few advantages over
standard simms; maximum access time of 35ns, with a minimum access time of 
15ns.Board space and circuitry for a separate L2 cache can be eliminated. A 
board thTtakes these simms could still accept standard 72 pin simms.
All memory added to the system is cached(with most systems, only the first 64mb
is cachable). The simms cost less than the simm/sram combo they replace. And of
course the most important advantage is that the system can run much faster 
with memory so fast. :)

The disadvantage? The cost more than regular simms. (I can't remember by how 
much... I believe around 20-30% though.)

Vince Reed
UCSF Cardiothoracic Surgery
vince@cardiothoracic.ucsf.edu
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