You (Russell Kent) wrote:
>
> 4. What about the RAMTRON EDRAM part? (DM 1M36SJ) It uses a JEDEC
> standard form (= least cost sockets), has a 512x36 integrated
> cache with a 2Kbit-wide interface to the DRAM (yowza!) so a
> cache-miss causes a 2048-bit cache fill in a 35ns cycle time.
> All memory access goes through the integrated cache, so cache
> coherency between the CPU and any funky DMA peripherals is a
> non-issue.
> Cons: - it's a 36-bit part, so they'd need to be added in pairs.
> - it's not the ubiquitous PC SIMM, so those folks who
> are/were planning to use PC SIMMs are out-of-luck.
> (or they run without cache: the RAMTRON DRAM controller
> handles standard SIMMs, too!)
> - it is not really a set-associative cache; it only has one
> working-set. This means that highly localized references
> win, but random accesses cause cache misses.
>
> That last con I think could be a killer. That and the cost of
> the part. Does anyone have a cost for the EDRAM?
35ns is still almost twice as fast as normal dram. If this is really the
cache-miss time this part sounds very interesting. I'm getting really
curious about its cost.
hp
--
_ | hp@vmars.tuwien.ac.at | Peter Holzer | TU Vienna | CS/Real-Time Systems
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| | | ...and it's finished! It only has to be written.
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