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L2 Caching and SIMMs format

To: riscy@sunsite.unc.edu
Subject: L2 Caching and SIMMs format
From: Daniel.Veillard@imag.fr (Daniel Veillard)
Date: Fri, 19 Nov 93 12:36:36 +0100
Cc: Danie.Veillard@imag.fr


  just a few remarks concerning The Board design :

- maybe we should put the L2 cache memory management 
  even if most of us won't use it (SRAM == $$$), in order
  to preserve the expandability of the beast. Upgrading
  to R4400 without L2 cache may not be very interesting.
- What format of SIMMs will be needed, 36 or 72 bits?
  I bet most of us spent much $$$ in 36 bit SIMMs and
  would be disapointed if these cannot fit onto their
  Super Board. But there is probably a bandwith problem
  with 36 bits SIMMs.

 Maybe the HW specialists here could comment on these points,

Daniel

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PS : my first posting failed due to a change in the way mail is
     managed here in Grenoble. I had to re-suscribe to the
     mailing list but I cannot remove my old adress :
     
>daniel.veillard@imag.fr: You are not subscribed to riscy@sunsite.unc.edu.
>Your message is returned to you unprocessed. If you want to subscribe,
>send mail to listserv@sunsite.unc.edu with the following request:
>
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>In addition, the system found the following address(es) that resemble yours.
>If one of these is you, please resend your message from that one, or use the
>'set <list> address' request to change the address you are subscribed with:
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>DANIEL.VEILLARD@IMAG.IMAG.FR
                 ^^^^^
could someone remove this old adress, please.

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Daniel Veillard :                | Bull-IMAG Systems
E-mail : Daniel.Veillard@imag.fr | Centre Equation
Tel : (33) 76 63 48 53           | 2 ave. de Vignates
Fax : (33) 76 54 76 15           | 38610 GIERES FRANCE
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