riscy
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Re: Second level cache?

To: riscy@pyramid.com
Subject: Re: Second level cache?
From: Andreas Busse <andy@resi.waldorf-gmbh.de>
Date: Wed, 11 Aug 93 11:49:06 +0200
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com
> What I understand is that the ARC chipset supports a secondary cache
> similar to the way it does for the 486.  It is not necessary to use
> the cache support signals from the R4k to have a secondary cache, although
> it may mean that this cache will take two cycles to access data where
> the R4000SC cache would take one.  This may not be great, but it is still
> better than the cycles required to get data from DRAM.

I really wonder from where the information comes that ARCset supports
any kind of 2nd level cache in its *true* sense.
I had a closer look the uPD31432 (Adress Path Controller) data sheet.
Quoted (Page 58,59):

5.1 Memory Interface Signal SUmmary

Signal Name             Description

MADR[10:0]              Multiplexed row and column adress lines.
                        Shared with video interface.
/MRAS[3:0]              Early Memory Row Adress Strobe. [...]
/MEM_CAS[A:D]           Four identical copies of early memory
                        Column Adress Strobes. [...]
/MWR_CMD                Memory Write Command.
MEM_DATA_OE             The uPD31431 memory data lines output enables.
MEM_DATA_LE             [...] Data latch enables [...]
/B_MASK                 Time multiplexed byte mask lines. Used during
                        memory and video partial write operations
                        originating at Vr4000. Also used for I/O operations.
BM_PHASE                Signal to provide the phase information required
                        to demultiplex the B_MASK line. [...]

5.2 uPD31432 Video Interface Signal Summary

Signal Name             Description

VIDEO_CMD[2:0]          Video command bus - Identifies the current
                        command being sent to the video interface.
                        [...]
VIDEO_ADR10             Video adress bit 10 is used with MADR[10:0] to
                        provide a time multiplexed 20bit adress to the
                        video interface.
VIDEO_RDY               Video ready is used by the video controller to
                        inform the uPD31432 chip that is has completed
                        the requested operation.

5.3 Memory System Transfers

Memory Operation         Description

32 byte read            Vr4000 32 byte cache block fill. [...]
                        I/O cache fill operation.
16 byte read            Vr4000 16 byte cache block fill. [...]
32 byte write           Vr4000 32 byte cache block flush. [...]
                        I/O full cache line flush
16 byte write           Vr4000 16 byte cache block flush. [...]
Read modify write       Vr4000 write partial [...]
                        I/O partial cache line flush
Memory Refresh          Refresh timing set in Refresh Rate Register

[end of qouted material]

Please note those I/O cache operations. These are operations are
I/O caching, what means that 32byte-blocks of data to be transfered
from or to I/O is cached in main memory.
This has ***nothing*** to do with 2nd level cache.
Next thing: The memory interface is a *true* DRAM interface.

Again, quoted from the data sheet. Here's the complete pinout:
[Page 147ff]

Signal Name             I/Otype Description

R4000_DAL[32:00]        I/O     Vr4000 mux'ed data/adress lines
R4000_CMD[8:0]          I/O     Vr4000 system interface command bus.
R4000_CMDP              I/O     Single bit even parity for command bus.
/R4000_EXTRQST          OUT     This is the external request line to
                                the Vr4000 processor. [...]
/R4000_RELEASE          IN      Vr4000 release indicates that Vr4000
                                has released the bus.
/R4000_RDY              OUT     Asserted by uPD31432 when ready to
                                accept a R4000 command.
/R4000_VALID_IN         OUT     The uPD31432 asserts this signal when
                                driving a command or data on the
                                Vr4000 interface.
/R4000_VALID_OUT        IN      The Vr4000 asserts this signal when
                                driving a command or data on the
                                Vr4000 interface.
R4000_RCLOCK            IN      50 MHz receive clock
R4000_TCLOCK            IN      50 MHz transmit clock
/B_MASK[7:0]            OUT     Contains the byte mask information
                                used during write partials [...]
BM_PHASE                OUT     Used to demultiplex /B_MASK[7:0]
CACHE_OP[2:0]           OUT     uPD31432 control bus used to control
                                the I/O cache.
BLK_NUM[2:0]            OUT     I/O Cache block number selects one of
                                eight cache blocks for current operation.
C_LINE                  OUT     The cache line selects the 128 bit cache
                                line in the cache block selected by
                                BLK_NUM.
DMA_BANK_SEL            OUT     The DMA bank select is used to select
                                a 64bit quantity from the selected
                                cache line.
C_LTCH_EN               OUT     The cache latch enable is used as the
                                latch enable for the selected cache data.
R4000_DP_OD[1:0]        OUT     The R4000_DAL output enable is used to
                                turn off the the Vr4000 system bus drivers.
IO_OP[2:0]              OUT     These lines contain encoded control
                                information from the uPD31432 to configure
                                the uPD31431 chips during 386 bus operations.
/INTR1                  IN      Vr4000 interrupt level 1
/INTR2                  IN      Vr4000 interrupt level 2
/INTR3                  IN      Vr4000 interrupt level 3
/INTR5                  IN      Vr4000 interrupt level 5
/MCT_INTR               OUT     I/O DMA channel interrupt
/TIMER_INTR             OUT     Interval Timer Interrupt
TIMER_CLK               IN      Interval Timer base clock
BANK_SEL                OUT     This signal is used to select a 64 bit bank
                                out of the 128bit memory line to drive on
                                the R4000_DAL.
WMEM_STATE[2:0]         OUT     uPD31431 Vr4000 write buffer control bus.
PAR_ERR[1:0]            IN      Memory parity error lines from each of the
                                two datapath chips.
/MRAS[3:0]              OUT     Main memory row adress strobe lines
/MWR_CMD                OUT     Main memory read/write control line.
/MEM_CAS[A:D]           OUT     Four copies of the same main memory
                                DRAM column adress strobe.
MEM_DATA_OE             OUT     The uPD31431 memory data output enable
MEM_DATA_LE             OUT     Memory data latch enable controls the
                                uPD31431 memory data latches. [...]
MADR[10:0]              OUT     Memory adress lines are multiplexed
                                system memory DRAM row and column address
                                lines.
VID_ADR10               OUT     Video address bit 10, used with MADR[10:0]
                                to from complete video address bus.
VIDEO_CLK               OUT     25 MHz output signal used to drive the
                                video interface
VIDEO_CMD[2:0]          OUT     Video command is used to encode the video
                                interface control bus.
VIDEO_RDY               IN      Video ready is used by the video system to
                                respond to a uPD31432 video command.
CLK386                  OUT     25 MHz (1/2 R4000_TCLOCK) clock used as
                                the 386 bus clock.
H386_ADR[23:02]         I/O     I/O adress bus. It is also used to source
                                a 3 bit encoded DMA acknowledge packet
                                during local DMA operations [...]
/H386_ADS               I/O     I/O bus address strobe.
/H386_BE[3:0]           I/O     I/O bus byte enables.
/H386_M_IO              OUT     I/O bus control signal; used to select
                                between 386 I/O bus I/O or memory space.
/H386_RDY               I/O     I/O bus slave ready signal. [...]
/H386_BUS_ERROR         OUT     I/O bus error signal. [...]
/H386_W_R               I/O     I/O bus read and write line. [...]
/H386D_C                OUT     I/O bus command line. Selects between
                                normal data cycles and command cycles.
                                Used only to perform a 386 compatible
                                interrupt acknowledge signal.
ADR[1:0]                OUT     The signals provide the low two addresses
                                used by local I/O devices.
DMA_REQ[7:0]            IN      These DMA request lines are used by the
                                local DMA devices to signal the availability
                                to accept or deliver data.
LDMA_TC                 OUT     Local DMA terminal count is used to signal
                                the acknowledged DMA operation has reached
                                its terminal count. [...]
/DMA_ACK_CNT            OUT     This signal is used to control the assertion
                                of the local device DMA line selected with
                                H386_ADR[4:2]
/LOCALIO                OUT     Local I/O is used to control the assertion
                                of the local device chip select selected
                                with H386_ADR[23:20]
/SLAVE_RD               OUT     Local device read strobe.
/SLAVE_WR               OUT     Local device write strobe.
L_HLDA                  OUT     LAN hold acknowledge. Used by the address
                                chip to grant a requesting local bus master
                                the remote bus.
L_HOLD                  IN      The LAN; used by a remote bus master to
                                request control of the remote bus.
EISA_BCLK               IN      EISA bus clock; received by the address chip
                                to synchronize EISA control lines and
                                operations.
E_HLDA                  OUT     EISA hold acknowledge; used to grant the
                                EISA chip set to take control of the remote
                                I/O bus.
E_HOLD                  IN      The EISA hold is used by the EISA chipsets
                                to request control of the remote I/O bus.
HGT16M                  IN      EISA address greater than 16MBytes. [...]
/REFRESH                IN      EISA refresh signal. [...]
/IO_BUS_REQ             OUT     I/O bus request. [...]
/EISA_CMD               IN      EISA command line. [...]
/EISA_EXRDY             OUT     EISA ready signal. [...]
/EISA_HLOCMEM           OUT     Driven when an EISA transfer into system
                                memory is recognized. [...]
EIS_MBURST              IN      EISA master burst. [...]
EISA_START              IN      EISA start. [...]
/RESET                  IN      Chip reset signal.
TEST                    IN      Chip test signal.
/MACHCHK                OUT     Machine check interrupt is used to signal
                                a catastrophic system error.

[end of qouted material]

Next, we have a look at the data path controller, uPD31431.
The data sheet tells us that this chip contains the I/O cache buffers
mentioned earlier.

qouted from the spec sheet, page 7:

3.4 I/O cache buffers
The I/O cache buffers provide the data storage for eight 128bit bidirectional
data buffers. The cache buffer has a 32bit read/write portto the I/O remote
bus and provide a 64bit bidirectional port to the memory data lines. [...]

[end of quoted material]


I hope it's clear now that this chip set *DOES NOT* support 2nd level
cache. What it does is providing a cache subsystem for I/O operations
which is a good idea, but has nothing to do with 2nd level cache.


Andy

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