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Re: Second level cache?

To: riscy@sword.eng.pyramid.com
Subject: Re: Second level cache?
From: caret@pyramid.com (Neil Russell)
Date: Tue, 10 Aug 93 13:16:51 PDT
In-reply-to: <9308101415.AA14388@cbfsb.cb.att.com>; from "Stephen P Hill +1 708 979 0366" at Aug 10, 93 2:12 pm
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com
Stephen P Hill writes:

> My $0.02:
> A second level cache would be really, really nice.  But it sounds 
> like it will be out of our price range.  Unless it proves 
> (somehow) to be cheep to have an unpopulated 2nd level cache 
> on the board, it is time to forget it.

From what I understand, the ARC chipset provides secondary cache
support.  So we could easily end up with unpopulated 2nd level
cache sockets for very small additional cost.

Neil Russell            (The wizard from OZ)
Pyramid Technology                      Email:  caret@pyramid.com
3860 N. First Street                    Voice:  (408) 428-7302
San Jose, CA 95134-1702                   FAX:  (408) 428-8845

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