riscy
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Re: R4xxx Cache size.

To: riscy@pyramid.com
Subject: Re: R4xxx Cache size.
From: Drew Eckhardt <drew@romeo.cs.Colorado.EDU>
Date: Tue, 10 Aug 1993 03:39:21 -0600
In-reply-to: Your message of "Tue, 10 Aug 1993 10:58:48 +0200." <9308100858.AA20798@resi.waldorf-gmbh.de>
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com
    
    Oh, please stop that noise. I don't know who told you that the
    cache size of a R4000 is limited to 32+32k. 

Like I said, what NEC is passing out as one of their data books. Generally,
these things are technically accurate, although I'm begining to have my 
doubts.

After reading a few more chapters of the data book including the 
one on caching, nothing beyond the number of virtual address bits 
used as a cache index in the author's examples seems to back this 
up.  In hindsight, the statement I summarized from the data book
doesn't really sanity check, in school you quickly learn that in
many (most?) classes you get reasonable grades by blindly reciting 
the text book contents and telling the instructors what they want
to hear :-(

    Can you tell me how it would then be possible to add a secondary cache ????

Again, I said *primary* cache size, which has nothing to do with 
the (presumably off chip) second level cache.

    If you would take a look at the R4200 layout, you would see that
    more than 70 percent of the chip space is used by rams !

I'd take a look at the R4200 layout, but the local NEC distributor
didn't get anything on the 4000 series chips until Friday, and still
won't say anything about pricing or the 4200 :-(
 

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