riscy
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Re: R4xxx Cache size, pedantic ramblings

To: riscy@pyramid.com
Subject: Re: R4xxx Cache size, pedantic ramblings
From: Drew Eckhardt <drew@romeo.cs.Colorado.EDU>
Date: Tue, 10 Aug 1993 02:46:06 -0600
In-reply-to: Your message of "Tue, 10 Aug 1993 09:00:03 +0200." <9308100700.AA22443@erasmus.et.tudelft.nl>
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com
    >
    >R4000 : 8K I, 8K D
    >R4400 : 16K I, 16K D
    >
    >The maximum imposed by the R4000 architecture is 32K each for the primary
    >cache.  I don't know about the 4200 since I don't have a data book in fron
   t
    >of me like I do for the NEC Vr4000 and Vr4400, PC, SC, and MC variants :-)
        
    Huh? Does that mean that the ARCHITECTURE defines a maximum CACHE size?

    According to current definitions here at the computer architecture group,
    cache size is an implementation aspect, and shouldn't be visible at the
    architectural level.

Other people or groups, have different definitions.  Many software 
people consider architecture to be a given combination of machine,
cpu, and operating system.  Some vendors consider it to be their
register and instruction set definitions, including bit fields
(BTW, if this were the case the limit would have been stated as
512K each for the primary caches), others consider it to be their 
implementation (NEC's data book seems to use this definition since 
it's not using one of the others)


According to 

_MIPS R4000 USER'S MANUAL_

by Joseph Heinrich

which happens to be what NEC is calling their 

VR4000-SERIES(tm)ARCHITECTURE
                 ^^^^^^^^^^^^
INCLUDING VR4400(tm)
USER'S MANUAL

under the "Processor General Features" heading of page 6 

"Cache Control,  The R4000 primary instruction and data caches reside on-chip, 
and can each hold 8K bytes.  In the R4400 processor, the primary caches can 
each hold 16K bytes.  Architecturally, each primary cache can be increased to
                      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
hold up to 32K bytes.  An off-chip secondary cache (R4000SC and R4000MC
^^^^^^^^^^^^^^^^^^^^
processors only) can hold from 128 Kbytes  to 4 Mbytes.  All processor
cache control logic, including the secondary cache control logic, is on
chip"

Their usage of "architecture" seems to indicate a usage refering 
to their implementation as perfectly acceptable.  What does it matter?  As 
long as the chip does what we want, I don't care what their definition of 
architecture is.

    -----
    This means that the R4xxx has a bad design: the design mixes implementation
    
    with architectural features. The R4000 isn't as clean as we thought. This
    means that we can't use the R4000 as the processor.... :-)

    -----

For those who care about the facts and not what definition of "architecture"
was used,  here are a few interesting factoids that would affect relative 
cache hit rates of an i486 (baseline) and our system...

1.  Primary I/D caches are separate.

2.  The 4000PC has 8K I/D caches, the biggest R4000 series chips SHIPPING have 
        16K I/D caches.

3.  The caches are direct mapped.

4.  Line size is user-configurable to either 16 or 32 bytes wide.

5.  The data cache can be write-back.

6.  All instructions are 32 bits.

Compare to the i486 if you want : 

1.  There is a single cache.

2.  The i486 has an 8K cache.

3.  The primary cache is set associative (I think  4-way).

4.  Primary cache line size is 16 bytes

5.  The primary cache is write-through.

6.  Some instructions are one byte, many are two-byte, 16 bit 
        accesses require a prefix in a 32 bit mode task, 
        other things require prefixes.

 

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