riscy
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Re: Second level cache?

To: riscy@pyramid.com
Subject: Re: Second level cache?
From: weingart@inf.ethz.ch
Date: Mon, 09 Aug 93 17:23:56 +0200
In-reply-to: Your message of "Mon, 09 Aug 93 09:13:39 MDT." <9308091513.AA10979@agua.colorado.edu>
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com
You write: 
Sie schreiben: 


>   > Any suggestions on how to get some numbers experimentally?
> 
> Yea build an R4000 system with the desired level of interleaving; one with
> and one without secondary cache. Then run both systems :)

Ok, I'll throw in my ballot for the cache one...

Can I "test-drive" for free?  ;-)


I don't know much about hardware design, but could you design the thing
in such a way that you can plug in cache, when you need it.  IE: if you
don't have the money, the board will run without the SC, and if you do,
you just buy some SRAM, and plug 'er in...

Or will this cause the logic to go beserk?

--Toby.
--------------------------------------------------------------
|Tobias Weingartner  |    PGP2.x Public Key available at     |
| +41'01'254'7205    |   'finger weingart@tau.inf.ethz.ch'   |
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%SYSTEM-F-ANARCHISM, the operating system has been overthrown
 

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