> > Also, there are algorithms that when combined with an instruction cache
> > (which our r3k's have) that will bitblt at 100% of the memory bandwidth
> > once the code is in the I-cache. That is, we can easily equal the
> > performance
> > of a hardware blt'er.
> >
> Maybe so, but in the meanwhile the processor cannot do diddly with your
> programs and kernel, so IMHO it's better to have a graphics coproc to
> cover the video part (that's what it's designed for) and leave the R3K do
> the real job: run programs.
That's what a memory-to-memory DMA is for, no? Of course, there's too
much overhead in setup for small blits with *either* a blitter or a
DMA channel, so they're best done with an algorithm that fits in the
cache.
Paul
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Paul Antoine, Softway Pty Ltd Net: paul@sw.oz.au
PO Box 305, Strawberry Hills, NSW 2012, Australia Tel: +61 2 698 2322
Level 2, 79 Myrtle St, Chippendale, NSW 2008, Australia Fax: +61 2 699 9174
"Proper management technique must include checking that all staff have
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