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MIPS 4000 cheaply!!!!

To: riscy@pyramid.com
Subject: MIPS 4000 cheaply!!!!
From: U001295@HNYKUN11.URC.KUN.NL (R. Schalk)
Date: Thu, 01 Jul 93 22:34:52 MET
Organization: Universitair Centrum Informatievoorziening
For those of you guys that cannot read netnews: I picked up this in c.o.l.
Read it good, maybe the R4K2 becomes a viable alternative, the only problem
I see is that it works at 3V and the price 55$ is great in comparison
to the R3K, I guess we should wonder if the R3K doesn't become obsolete.
I mean how long will it be produced, the same is happening now with the
386sx and 386dx, they are either out of production, or soon to be dropped.
I'm totally guessing now, but how long does this project take, half a year?
I guess that's not discussed yet, I believe.

Ronald Schalk

>Here is a news article from Byte Magazine,
>July 1993, p28.  Copyright (c) 1993 by McGraw-Hill, Inc.
>
>LOW-POWER RISC FROM MIPS
>
>Promising "Pentium performance in a notebook,"
>Mips Technologies (Mountain View, CA) has announced
>the first power-saving chip in its R4000
>microprocessor family, an important step toward
>moving RISC chips from workstations to mainstream PCs.
>The R4200 is intended primarily for laptops that
>can run Windows NT.
>  Sample silicon wasn't available at press time, so
>all performance specifications are preliminary.
>According to Mips, the 3-V chip will use only 1.5 W at
>its top internal clock speed of 80 MHz (the external
>bus runs at 40 MHz).  A reduced-power mode
>requires only 0.4 W, and a power-down mode turns
>off the chip altogether.  Mips says the R4200 can be
>powered down and reactivated so quickly that a
>system could force the chip into power-down mode
>between keystrokes when you're typing.
>  Mips estimates the R4200 will deliver 55 SPECmarks
>for integer operations (SPECint92) and 30 SPECmarks
>for floating-point operations (SPECfp92).
>By contrast, Intel's Pentium delivers
>64.5 SPECint92 and 56 SPECfp92, respectively.
>The R4200 lacks the parallel pipelines found in
>the Pentium, but it does have separate hardware units
>for integer and floating-point instructions.
>  Based on 0.6-micron process technology, the
>R4200 squeezes 1.3 million transistors onto a small
>die of 9.2 by 9.8 millimeters.  It has a 16-KB
>instruction cache and an 8-KB data cache.  The caches,
>MMU (memory management unit), and system interface
>can be removed from the chip, so the logic
>core can be used in embedded applications.
>  Mips says the R4200 will be available in quantity
>late this year.  Versions will be manufactured by
>Mips, NEC Electronics, and possibly other partners.
>No pricing was announced, but Mips says the goal
>is to sell the chip for $55, or $1 per SPECint.
>                     -- Tom R. Halfhill
>(transcription and posting by Larry Doolittle doolittle@cebaf.gov)
>(I actually got written permission from Byte to post this!)
>
Greetings Ronald Schalk


 ********************************************************************
 * ing. Ronald Schalk                                               *
 * sectie COOS                                                      *
 * Universitair Centrum Informatievoorziening (UCI)                 *
 * Katholieke Universiteit Nijmegen (KUN)                           *
 * e-mail : R.Schalk@uci.kun.nl   snailmail: Geert Grooteplein 41   *
 * tel.   : +31 80 617993                    6525 GA Nijmegen       *
 * fax   :  +31 80 617979                    Nederland              *
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