From: firstname.lastname@example.org (Neil Russell)
Date: Sat, 3 Jul 93 21:27:23 PDT
In my opinion, Adaptec have one of the best SCSI controllers that you
can get for a PC like machine. Why is it good? It provides master
DMA, scatter/gather modes, etc.
Sounds great, but you forgot to mention the part number! :-)
If I interpreted his post correctly, he was refering to the 1542 ISA
controllers, built arround Adaptec's own chip, and commenting how
all of the features that made it great were not needed on our
system (especially with the Adaptec's $200 price tag).
I've never seen an Adaptec chip on a non-adaptec product, and the chip
probably isn't suited to what we need. Personally, I like the NCR53c90A/
NCR53cf90 chips. Not nearly as hard to interface as the 53c700 series,
not as hard to program (the 53c700 series have onboard microcontrolllers,
and are best programmed with NCR's SCRIPTS development tools), not as
featureful but probably well suited to our purposes. In case you
missed it, here's my posting regarding the chip :
(BTW, a QFP which would use less realestate is also available,
there are also a 53c94/53cf94 chips which offer a 8 or 16 bit
wide bus (you have to demux it though), I'm not sure about
pricing on these)
Ok, I called NCR's SCSI division, got some literature on the 53c90
series, saw that the 53c90 looks like what we wanted, and talked to
the local NCR distributor, Electrodyne (303)-695-903 for pricing
The NCR 53c90(A or B) can sustain 6M/sec asynchronous on a one
foot cable, worst case 4.5M/sec on a one foot cable,
3M/sec on a maximum length (single ended) cable (provided
that the internal drivers are used. Note that asynch. SCSI
is only spec'd to 2.3M/sec, and for higher transfer rates
sync. SCSI must be used). It also does sync. SCSI to 5M/sec.
A fast version of the chip is also available, I'm less clear
on it's specs.
The controller is totally integrated, ie there are onchip
SCSI drivers, etc - we only need to add decode circuitry
and a 25Mhz clock (Ok, technically it requires a 10Mhz clock
for async, 12 Mhz for sync, but the sync. SCSI clock
is derived from the external clock and the minimum divisor
is five - so we need a 25Mhz crystal oscilator for this thing
to get 5M/sec sync. SCSI).
It comes in a 68 lead PLCC, .910" square.
The host/DMA interface is 8 bits wide, so it's best on an
8 bit bus of the 3730.
The controller is semi-intelligent, ie it supports
commands to "arbitrate, select, send message, then 6,10,
or twelve command bytes and generate interrupt when
done", "transfer information", "return status byte
followed by message byte". In the normal case,
we'll service four interrupts per command (one for "Select
with ATN sequence", one when reselection completes,
one for information transfer complete, one for command
complete). We'll set up for one DMA transfer per command.
(Essentially all I/O can be done directly by
the CPU or the DMA, except for sync. SCSI DATAIN/DATAOUT
which can only be transfered via DMA) - either one through the
16 byte FIFO buffer. Personally, I'd DMA the DATAIN/DATAOUT
SCSI phases so we only have the overhead of one DMA controller
setup, the command bytes, message / status in, etc will fit in the
16 byte FIFO buffer.
1-49 : $17.60
50-99 : $16.35
( In light of this, we definately want to go with the cf flavor)
50-99 : $18.60
100-999 : $16.80
Important question :
With SCSI, you want to minimize the command overhead per block, so
you want to read/write the maximum number of blocks per command. How
ever, buffer-cache is non-contiguous, so you need scatter-gather-support
to do it.
Without scatter/gather, you end up doing one read/write per
block and performance can be quite abysmal (as in, before we
implemented scatter-gather in the Linux SCSI code, we saw
60K/sec through the file system, after 500-700K/sec on
Seagates, more on reasonable hardware).
So : Does the 3051/3081 / 3730 combination support DMA to non-contiguous
pieces of memory for one DMA transfer? (With motorola 68k machines,
DMA is done through the paging unit so this is automatic,
Intel doesn't do it which is why all decent PC SCSI boards must bu$ ma$ter)?
Right now the SCSI disk driver tries for a 16 sector readahead (ie, 8K),
this is small enough so that we can DMA directly to an intermediate
buffer and copy it back on the interrupt we recieve after the information
transfer phase is complete, so I retract my whining about scatter/gather