riscy
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Main CPU and Peripheral controller

To: riscy@pyramid.com
Subject: Main CPU and Peripheral controller
From: caret@pyramid.com (Neil Russell)
Date: Sat, 3 Jul 93 21:26:15 PDT
Reply-to: riscy@pyramid.com
Sender: riscy-request@pyramid.com
In my original design, I had planned to use the IDT 79R3730 "Raster
Image Processor".  IDT's intended market for the device is the
Laser Printer market, however the chip lends itself to our design
quite nicely.  In the 1992/1993 Data Book entitled "RISC Microprocessor
Components & SubSystems", there is Advance information on the 3730.
The following is copied from it:

  FEATURES:
        *  Integrated System Controller(TM) for the IDT R3051
           family Raster Image Processors and Laser Printer
           Controllers:
             -  Direct interface to R3041, R3051, R3052 and R3081
             -  Supports clock frequencies to 40 MHz.
        *  High-Performance, programmable DRAM controller:
             -  Flexible DRAM control for up to 128 MB of two-way
                interleaved or non-interleaved DRAM (up to 8 banks)
             -  Wide variety of memory configurations (eg. different
                sized DRAMs for base and SIMM extensions)
             -  DMA channel for memory pattern fill/clear
             -  DRAM parity generation/checking
        *  Programmable I/O ports support glue-less interface to
           support low-cost peripherals:
             -  Burst DMA channels with chaining
             -  On-chip 4-word x 32-bit FIFOs with data packing
                and unpacking
             -  Master/slave peripheral interface
             -  8-bit and 16-bit I/O ports.
        *  Co-processor DMA interface for accelerator ASICs
           (eg. Adobe's Type 1 font rasterizer and PixelBurst(TM)
           display list processor)
        *  Programmable Interrupt Controller
        *  High-performance programmable video interface
             -  1, 2 or 4 serial video streams support high video
                bandwidth (bi-level or 4-bit color)
             -  Video DMA channels with chaining
             -  On-chip 8-word x 32-bit video FIFO
             -  Programmable margin counters
             -  Video bit rates to 160 mega-bits per second
             -  Supports split stream video
             -  PEL counter
        *  Controls for ROM memory system
             -  Programmable controls for up to 24 MB of interleaved
                or non-interleaved ROM/EPROM (up to 6 banks)
             -  Burst ROM/EPROM support
             -  Glue-less interface for 8-bit boot ROM or EPROM
        *  General purpose functions
             -  Bus timeout counter
             -  Rotate assist (0, 90, 180, 270 degrees and mirror)
                hard-ware
             -  General purpose counter/timer
             -  Bit programmable I/O port.


To rephrase all this into what this means for us:

        *  Our DRAM interface can be two-way interleaved (which means
           that 64-bits of memory are accessed each memory cycle, so
           that the CPU will have the data for its next read already
           in the data buffers, which reduces every second access to
           1-cycle instead of about 6-cycles), DRAM page mode and
           early-write modes can be taken advantage of to further
           speed up access.
        *  The interface to the DRAM is reduced to a handful of
           buffers and bi-directional latches; there is no logic
           for address decoding.
        *  DRAM refresh is taken care of.
        *  There are two extra busses provided by the 3730:  an
           8-bit one and a 16-bit one.  Each bus has a small address
           bus in addition to its data bus.  The processor can
           access devices on these busses directly with the 3730 taking
           care of the data-size/endian issue automatically.  If
           a DMA is setup to a device on one of these busses, the
           main memory bus is not held up waiting for the slower
           devices to respond.  The 3730 will do a burst DMA into
           main memory whenever there is sufficient data.
        *  Any of the DMA channels can be chained, which means (if
           I understand this correctly) we can do scatter/gather.
           (All this would make the SCSI interface almost trivial).
        *  Glue for an extend bus (such as ISA) would require very
           little additional support.


I talked to IDT on Friday (July 2) and have some more information about
the IDT R3730.

First the good news:  They have already made the first production run
of wafers of this chip.  They expect that the chip will be in the
stores :-) by October.  The salesman I spoke to is willing to provide
an information package this week.

Now the bad news:  The chip is only available in a 208 pin FQFP (a
surface mount package).  The pricing is us$50 - us$70 in lots of
5,000.  This would translate to >us$100 for the quantities that
we want.

However, there have been some developments in the last week or so
that may mean that Surface Mount is OK.  More on that as details
are available.


Alternatives
------------

If we cannot use the 3730, there is another alternative that was
thought up by Steven Ligett, Jerry Callen (and Pat Mackinlay?).

This involves creating a DRAM interface between the main CPU and
memory using programmable logic.  This interface would provide:

        *  DRAM address multiplexing
        *  Two-way interleaving
        *  Page mode support
        *  Early write mode support
                (The last three are provided on the special CPU
                 cycles only, such as the instruction cache refill).

There would be a R3041 co-processor connected to the main CPU via a DMA
channel.  The only connection to the outside world for the main CPU
would be this co-processor.

Information copied from the IDT data book on the 3041:

   FEATURES:
        *  Instruction set compatible with IDT 79R3000A and R3051(TM)
           family RISC CPUs
        *  High level of integration minimizes system cost:
             -  RISC CPU
             -  Multiply/divide unit
             -  Instruction cache
             -  Data cache
             -  Programmable bus interface
             -  Programmable port width support
        *  On-chip instruction and data caches:
             -  2 KB of instruction cache
             -  512 bytes of data cache
        *  Flexible bus interface allows simple, low cost designs
             -  Superset pin-compatible with R3051
             -  Adds programmable port width interface
                (8-bit, 16-bit and 32-bit memory sub-regions)
             -  Adds programmable bus interface timing support
                (Extended address hold, bus turn around time,
                 read/write masks)
        *  Single, double frequency clock input
        *  16 or 20 MHz operation
        *  14 MIPS at 20 MHz
        *  Low cost 84-pin PLCC packaging
        *  On-chip 4-deep write buffer eliminates memory write stalls
        *  On-chip 4-word read buffer supports burst or simple block reads
        *  On-chip DMA arbiter
        *  On-chip 24-bit timer
        *  Boot from 8-bit, 16-bit or 32-bit wide boot ROMs

The 3041 essentially does in software what the 3730 does in hardware,
with the added flexibility that its very programmable.  As an example,
if the 3041 was given a scatter/gather SCSI disk access to do, it
would read/write the data directly top the SCSI port, and write/read
the data to the appropriate location in the main CPUs memory.


Some costings:

    3730:
        3730    about $120 or more (see above)
        glue    about $10 (buffers, latches, one of two PALs)

    3041:
        3041    about $35
        glue    about $30 (buffer, latches, lots of PALs)
        memory  about $45 (maybe those old 256K SIMMS?)


Advantages of 3730:
        -  Single chip does almost everything
        -  Not much R&D to get it going
Disadvantages of 3730:
        -  Cost (maybe; can't tell until October)
        -  Availability
Advantages of 3041:
        -  Parts are available now
        -  Cost
        -  More programmable (RISC does it in software approach)
Disadvantages of 3041:
        -  More R&D
        -  Lots of hard real time software to write
        -  More board space needed.

(Note:  If video is provided on the motherboard and connected to the 3041,
        then maybe some of the unused space in the VRAM could be used as
        program memory for the 3041, further reducing the cost.)


My opinion is that we should dump the 3730 and use the 3041 approach.
The cost of the extra board space is offset by the reduction in cost
of the sub-system, and the parts are available *now*.


Comments?


For you interest, this is the blurb for the R3081 (the proposed main CPU):

    FEATURES:
        *  Instruction set compatible with IDT 79R3000A, R3051 and
           R3500 RISC CPUs
        *  High level of integration minimizes system cost
             -  R3000A Compatible CPU
             -  R3010A Compatible FPU
             -  Optional R3000A compatible MMU [E suffix - ed]
             -  Large instruction cache
             -  Large data cache
             -  Read/write buffers
        *  35 VUPS at 40 MHz
             -  64,000 Dhrystones
             -  11 MFlops
        *  Flexible bus interface allows simple, low cost designs
        *  Optional 1x or 2x clock input
        *  20, 25, 33 or 40 MHz operation
        *  "L" version operates at 3.3V [this saves power - ed]
        *  Large on-chip caches with user configurability
             -  16 KB Instruction cache, 4 KB data cache
             -  Dynamically configurable to 8 KB instruction cache
                and 8 KB data cache
             -  Parity protection over data and tag fields
        *  Low cost 84-pin packaging
        *  Super-set compatible with the R3051
        *  Multiplexed bus interface with support for low-cost,
           low-speed memory systems with a high speed CPU
        *  On-chip 4-deep write buffer eliminates memory write stalls
        *  On-chip 4-deep read buffer supports burst or simple block reads
        *  On-chip DMA arbiter
        *  Hardware-based cache coherency support [snooping cache - ed]
        *  Programmable power reduction mode
        *  Bus interface can operate at half-processor frequency
-- 
Neil Russell            (The wizard from OZ)
Pyramid Technology                      Email:  caret@pyramid.com
3860 N. First Street                    Voice:  (408) 428-7302
San Jose, CA 95134-1702                   FAX:  (408) 428-8845

 

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